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参数资料
| 型号： | MC100ES6222TBR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | PLASTIC, LQFP-52 |
| 文件页数： | 1/9页 |
| 文件大小： | 314K |
| 代理商： | MC100ES6222TBR2 |
7
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES6222/D
Rev 1, 11/2002
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
712
Low Voltage 1:15 Differential
ECL/PECL Clock Divider and
Fanout Buffer
The Motorola MC100ES6222 is a bipolar monolithic differential clock
fanout buffer. Designed for most demanding clock distribution systems,
the MC100ES6222 supports various applications that require the distribu-
tion of precisely aligned differential clock signals. Using SiGe technology
and a fully differential architecture, the device offers very low skew out-
puts and superior digital signal characteristics. Target applications for this
clock driver is high performance clock distribution in computing, network-
ing and telecommunication systems.
Features
15 differential ECL/PECL outputs (4 output banks)
2 selectable differential ECL/PECL inputs
Selectable ÷1 or ÷2 frequency divider
130 ps maximum device skew
Supports DC to 3 GHz input frequency
Single 3.3V, -3.3V, 2.5V or -2.5V supply
Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP222
Functional Description
The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The
CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and
six differential clock output pairs can be independently configured to distribute the input frequency or
÷2 of the input frequency.
The FSELA, FSELB, FSELC, FSELD and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a
MR pulse for resynchronization of the the
÷2 outputs. For the functionality of the MR control input, see Figure 5, “Functional
Diagram,” on page 718.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if
only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6222 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the
MC100ES6222 supports positive (PECL) and negative (ECL) supplies. The MC100ES6222 is pin and function compatible to the
MC100EP222.
MC100ES6222
LOW–VOLTAGE
1:15 DIFFERENTIAL
ECL/PECL CLOCK DIVIDER
AND FANOUT DRIVER
TB SUFFIX
52–LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC100ES6226AC | 功能描述:时钟缓冲器 FSL 1-9 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MC100ES6226ACR2 | 功能描述:时钟驱动器及分配 FSL 1-9 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC100ES6226FA | 功能描述:时钟缓冲器 Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MC100ES6254AC | 功能描述:时钟驱动器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC100ES6254ACR2 | 功能描述:时钟驱动器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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