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参数资料
| 型号： | MC100ES6222TBR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | PLASTIC, LQFP-52 |
| 文件页数： | 9/9页 |
| 文件大小： | 314K |
| 代理商： | MC100ES6222TBR2 |
7
MC100ES6222
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
720
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100ES6222
The MC100ES6222 uses a thermally enhanced exposed
pad (EP) 52 lead LQFP package. The package is molded so
that the leadframe is exposed at the surface of the package
bottom side. The exposed metal pad will provide the low ther-
mal impedance that supports the power consumption of the
MC100ES6222 high-speed bipolar integrated circuit and
eases the power management task for the system design. A
thermal land pattern on the printed circuit board and thermal
vias are recommended in order to take advantage of the en-
hanced thermal capabilities of the MC100ES6222. Direct sol-
dering of the exposed pad to the thermal land will provide an
efficient thermal path. In multilayer board designs, thermal vias
thermally connect the exposed pad to internal copper planes.
Number of vias, spacing, via diameters and land pattern de-
sign depend on the application and the amount of heat to be
removed from the package. A nine thermal via array, arranged
in a 3 x 3 array and using a 1.2 mm pitch in the center of the
thermal land is a requirement for MC100ES6222 applications
on multi-layer boards. The recommended thermal land design
comprises a 3 x 3 thermal via array as shown in Figure 7 “Rec-
ommended thermal land pattern”, providing an efficient heat
removal path.
4.8
Figure 7. Recommended thermal land pattern
Thermal via array (3x3),
1.2 mm pitch,
0.3 mm diameter
Exposed pad
land pattern
all units mm
4.8
The via diameter is should be approx. 0.3 mm with 1 oz.
copper via barrel plating. Solder wicking inside the via resulting
in voids during the solder process must be avoided. If the cop-
per plating does not plug the vias, stencil print solder paste
onto the printed circuit pad. This will supply enough solder
paste to fill those vias and not starve the solder joints. The
attachment process for exposed pad package is equivalent to
standard surface mount packages. Figure 8 “Recommended
solder mask openings” shows a recommend solder mask
opening with respect to the recommended 3 x 3 thermal via
array. Because a large solder mask opening may result in a
poor release, the opening should be subdivided as shown in
Figure 8 For the nominal package standoff 0.1 mm, a stencil
thickness of 5 to 8 mils should be considered.
Exposed pad
land pattern
4.8
Figure 8. Recommended solder mask openings
Thermal via array (3x3),
1.2 mm pitch,
0.3 mm diameter
1.0
0.2
all units mm
4.8
1.0
0.2
For thermal system analysis and junction temperature cal-
culation the thermal resistance parameters of the package is
provided:
Table 9. Thermal Resistancea
Convection-
LFPM
RTHJAb
°C/W
RTHJAc
°C/W
RTHJC
°C/W
RTHJBd
°C/W
Natural
20
48
100
18
47
4e
200
17
46
4e
29f
16
400
16
43
29f
800
15
41
a. Applicable for a 3 x 3 thermal via array
b. Junction to ambient, four conductor layer test board
(2S2P), per JES51-7 and JESD 51–5
c. Junction to ambient, single layer test board, per JESD51-3
d. Junction to board, four conductor layer test board (2S2P)
per JESD 51-8
e. Junction to exposed pad
f. Junction to top of package
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations to
their particular application. The exposed pad of the
MC100ES6222 package does not have an electrical low im-
pedance path to the substrate of the integrated circuit and its
terminals. The thermal land should be connected to GND
through connection of internal board layers.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC100ES6226AC | 功能描述:时钟缓冲器 FSL 1-9 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MC100ES6226ACR2 | 功能描述:时钟驱动器及分配 FSL 1-9 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC100ES6226FA | 功能描述:时钟缓冲器 Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MC100ES6254AC | 功能描述:时钟驱动器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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