Analog to Digital (ATD) Module
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor
20-5
Analog source capacitance (CAS) — This is the filtering capacitance on the analog input, which (if
large enough) may help the analog source network charge the ATD input in the case of high RAS.
ATD input resistance (RAIN – maximum value 7 kΩ) — This is the internal resistance of the ATD
circuit in the path between the external ATD input and the ATD sample and hold circuit. This
resistance varies with temperature, voltage, and process variation but a worst case number is
necessary to compute worst case sample error.
ATD input capacitance (CAIN – maximum value 50 pF) — This is the internal capacitance of the
ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process
variation but a worst case number is necessary to compute worst case sample error.
ATD conversion clock frequency (fATDCLK – maximum value 2 MHz) — This is the frequency of
the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler.
This frequency determines the width of the sample window, which is 14 ATDCLK cycles.
Input sample frequency (fSAMP) — This is the frequency that a given input is sampled.
Delta-input sample voltage (
ΔV
SAMP) — This is the difference between the current input voltage
(intended for conversion) and the previously sampled voltage (which may be from a different
channel). In Non-continuous Convert Mode, this is assumed to be the greater of (VREFH – VAIN)
and (VAIN – VREFL). In Continuous Convert Mode, 5 LSB should be added to the known difference
to account for leakage and other losses.
Delta-analog input voltage (
ΔV
AIN) — This is the difference between the current input voltage and
the input voltage during the last conversion on a given channel. This is based on the slew rate of
the input.
In cases where there is no external filtering capacitance, the sampling error is determined by the number
of time constants of charging and the change in input voltage relative to the resolution of the ATD:
# of time constants (
τ) = (14 / f
ATDCLK) / ((RAS + RAIN) * CAIN)
Eqn. 20-1
sampling error in LSB (ES) = 2
N * (
ΔV
SAMP / (VREFH - VREFL)) * e
τ
The maximum sampling error (assuming maximum change on the input voltage) will be:
ES = (3.6/3.6) * e
–(14/((7 k + 10 k) * 50 p * 2 M)) * 1024 = 0.271 LSB
Eqn. 20-2
In the case where an external filtering capacitance is applied, the sampling error can be reduced based on
the size of the source capacitor (CAS) relative to the analog input capacitance (CAIN). Ignoring the analog
source impedance (RAS), CAS will charge CAIN to a value of:
ES = 2
N * (
ΔV
SAMP / (VREFH – VREFL)) * (CAIN / (CAIN + CAS))
Eqn. 20-3
In the case of a 0.1
μF C
AS, a worst case sampling error of 0.5 LSB is achieved regardless of RAS.
However, in the case of repeated conversions at a rate of fSAMP, RAS must re-charge CAS. This recharge is
continuous and controlled only by RAS (not RAIN), and reduces the overall sampling error to:
ES = 2
N * {(
ΔV
AIN / (VREFH – VREFL)) * e
(1 / (f
SAMP
* R
AS
* C
AS
)
+ (
ΔV
SAMP / (VREFH - VREFL)) * Min[(CAIN / (CAIN + CAS)), e
(1 / (f
ATDCLK
* (R
AS
+ R
AIN
) * C
AIN
)]}
Eqn. 20-4
This is a worst case sampling error which does not account for RAS recharging the combination of CAS
and CAIN during the sample window. It does illustrate that high values of RAS (>10 kΩ) are possible if a