MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor
4-9
4.7.2
MCU SPI Pin Controls
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
4.7.2.1
SPSCK1 — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input (not allowed). When the SPI is enabled
as a master, this pin is the serial clock output (desired mode).
4.7.2.2
MOSI1 — Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not Bidirectional Mode), this
pin is the serial data output (desired mode).
When the SPI is enabled as a slave (not allowed) and SPC0 = 0, this pin is the serial data input. If SPC0 = 1
to select single-wire Bidirectional Mode, and Master Mode is selected, this pin becomes the bidirectional
data I/O pin (MOMI). Also, the Bidirectional Mode output enable bit determines whether the pin acts as
an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and Slave Mode is selected, this pin is
not used by the SPI and reverts to being a general-purpose port I/O pin.
4.7.2.3
MISO1 — Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not Bidirectional Mode), this
pin is the serial data input (desired mode).
When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data output. If SPC0 = 1 to select
Single-wire Bidirectional Mode, and Slave Mode is selected, this pin becomes the bidirectional data I/O
pin (SISO) and the Bidirectional Mode output enable bit determines whether the pin acts as an input
(BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and Master Mode is selected, this pin is not used
by the SPI and reverts to being a general-purpose port I/O pin.
4.7.2.4
SS1 — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input (not allowed).
When the SPI is enabled as a master and mode fault enable is off (MODFEN = 0), this pin is not used by
the SPI and reverts to being a general-purpose port I/O pin (desired mode) PTE2. When the SPI is enabled
as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the
mode fault input (SSOE = 0) or as the slave select output (SSOE = 1).
4.7.3
MCU SPI Interrupts
There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit