Modem SPI Register Descriptions
MC1321x Reference Manual, Rev. 1.6
5-28
Freescale Semiconductor
Bit 10
attn_irq — The Attention Interrupt bit indicates the ATTN pin
has been asserted or Power-up complete condition from a
reset condition.
The bit being set indicates the ATTN signal has
been asserted low or that the
MC1321x has
reached a Power-up complete condition after
software reset (CE released) or a hardware
reset (RST released).
Bit 9
doze_irq — The Doze Timer Interrupt bit.
This bit gets set when the ‘tmr_cmp2[23:0]’ field
matches the current Event Timer value while in
Doze Mode. The
MC1321x returns to Idle
state from Doze Mode.
Bit 8
tmr1_irq — The Timer Compare 1 Interrupt bit.
This bit gets set when the ‘tmr_cmp1[23:0]’ field
matches the current Event Timer value.
Bit 7
rx_ rcvd_irq or rx_strm_irq — The RX Packet Received
Interrupt or RX Stream Data Ready Interrupt bit is a
multiplexed interrupt status bit
When SPI bit use_strm_mode, Register 7, Bit 5
= 0, Register 24, Bit 7 represents ‘rx_rcvd_irq’.
rx_rcvd_irq definition: RX Packet Mode
reception complete and transceiver has returned
to Idle Mode.
When SPI bit use_strm_mode, Register 7, Bit 5
= 1, Register 24, Bit 7 represents ‘rx_strm_irq’.
rx_strm_irq definition:
1) First occurrence - RX Packet Length is
available to be read.
2) Subsequent occurrences - next receive
Stream data word is ready to be read.
Bit 6
tx_ sent_irq or tx_strm_irq — The TX Packet Sent Interrupt
or TX Stream Data Needed Interrupt bit is a multiplexed
interrupt status bit.
When SPI bit use_strm_mode, Register 7, Bit 5
= 0, Register 24, Bit 6 represents ‘tx_sent_irq’.
tx_sent_irq definition: TX Packet Mode
operation complete and transceiver has
returned to Idle Mode.
When SPI bit use_strm_mode, Register 7, Bit 5
= 1, Register 24, Bit 7 represents ‘tx_strm_irq’.
tx_strm_irq definition: Transceiver is ready for
next Stream transmit data word to be written.
Bit 5
cca_irq — The Clear Channel Assessment Ready Interrupt
bit.
This bit is set when the ‘Clear Channel
Assessment’ operation is complete.
Bit 4
tmr3_irq — The Timer Compare 3 Interrupt bit.
This bit gets set when the ‘tmr_cmp3[23:0]’ field
matches the current Event Timer value.
Bit 3
tmr4_irq — The Timer Compare 4 Interrupt bit.
This bit gets set when the ‘tmr_cmp4[23:0]’ field
matches the current Event Timer value.
Bit 2
tmr2_irq — The Timer Compare 2 Interrupt bit.
This bit gets set when the ‘tmr_cmp2[23:0]’ field
matches the current Event Timer value, or
alternately if ‘tc2_prime[15:0]’ field matches the
current Event Timer[15:0] when enabled.
Table 5-29. Register 24 Description (continued)
Name
Description
Operation