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参数资料
| 型号： | MC13852EPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | IC RF LNA 400MHZ-1GHZ 8 MLPD |
| 标准包装： | 1 |
| 频率： | 400MHz ~ 1GHz |
| P1dB： | 9.6dBm |
| 增益： | 18.3dB |
| 噪音数据： | 1.2dB |
| RF 型： | 通用 |
| 电源电压： | 2.3 V ~ 3 V |
| 电流 - 电源： | 5.5mA |
| 测试频率： | 900MHz |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | MC13852EPR2DKR |
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Applications Information
Table 6. Typical 434 MHz Evaluation Board Performance (Vcc = 2.75V, TA = 25 ° C) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Return Loss
High Gain
Bypass
S11
—
—
-5.5
-17.2
-4.5
-15.5
dB
Gain
High Gain
Bypass
S21
18.3
-9.3
19.3
-8.3
—
—
dB
Reverse Isolation
High Gain
Bypass
S12
—
—
-35
-8.3
-32
-7.3
dB
Output Return Loss
High Gain
Bypass
S22
—
—
-13.9
-20.4
-11
-19
dB
3.2
900 MHz Application
This application circuit is designed to demonstrate performance at 900 MHz. Typical results of
NF = 1.2 dB, S21 gain = 18.5 dB, and OIP3 of 14.2 dBm.
By varying the value of resistor R1, the current draw and IP3 performance of the device can be tailored for
a particular application. Two values of bias resistor R1 are shown to demonstrate performance for different
IP3 and Icc requirements.
? Resistor R3 is used to de-Q output inductor L2 and adjust gain and return losses. Reducing R3
lowers gain and improves return losses.
? Inductor L1 can be raised in value at lower current operation to improve return losses.
Typical performance that can be expected from this circuit at 2.75 V is listed in Table 7 .
Figure 8 is the 900 MHz application schematic with package pinouts and the circuit component topology.
L3
270 nH
L2
C3
.01u
pF
C4
33 pF
Vcc
10 nH
Enable
5
4
R2
C2
Gain
6
Logic
3
20 ohm 2.4 pF
RF
OUT
R3
200 ohm
RF IN
L1
12 nH
C1
3.9 pF
7
8
2
1
R1
1.2 kohm
Rbias
.
Figure 8. 900 MHz Application Schematic
MC13852 Advance Information, Rev. 2.0
Freescale Semiconductor
11
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