参数资料
型号: MC33186VW1
厂商: Freescale Semiconductor
文件页数: 20/24页
文件大小: 0K
描述: IC DRIVER H-BRIDGE 20-HSOP
标准包装: 1
类型: 半桥
输入类型: 非反相
输出数: 2
导通状态电阻: 150 毫欧
电流 - 输出 / 通道: 5A
电流 - 峰值输出: 6.5A
电源电压: 5 V ~ 28 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.433",11.00mm 宽)裸露焊盘
供应商设备封装: 20-HSOP
包装: 管件
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33186VW
20-PIN
HSOP-EP
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33186 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
Package and Thermal Considerations
The MC33186 is offered in a 20 pin HSOP exposed pad, single die package.
There is a single heat source (P), a single junction temperature (T J ), and thermal
resistance (R ? JA ).
VW SUFFIX (Pb-FREE)
T J
=
R ? JA
.
P
98ASH70273A
20-PIN HSOP-EP
Note For package dimensions, refer to
the 33186 data sheet.
Standards
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-
specific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
Table 6. Thermal Performance Comparison
1.0
Thermal Resistance
[ ? C/W]
0.2
R ? JA
29
1.0
R ? JB (2) , (3)
R ? JA (1) , (4)
9.0
69
0.2
* All measurements ?
R ? JC (5) 2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air condition.
2. 2s2p thermal test board per JEDEC JESD51-5 and ?
JESD51-7.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
20 Pin HSOP-EP
1.6 mm Pitch
16.0 mm x 11.0 mm Body
12.3 mm x 7.1 mm Exposed Pad
are in millimeters
Soldermast ?
openings
Thermal vias ?
connected to top ?
buried plane
5. Thermal resistance between the die junction and the exposed
pad surface; cold plate attached to the package bottom side,
Figure 28. Thermal Land Pattern for Direct Thermal
Attachment According to JESD51-5
remaining surfaces insulated.
33186
Analog Integrated Circuit Device Data ?
20
Freescale Semiconductor
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