参数资料
型号: MC33689DDWB
厂商: Freescale Semiconductor
文件页数: 3/31页
文件大小: 0K
描述: IC SYSTEM BASE W/LIN 32-SOIC
标准包装: 42
应用: 自动镜像控制
接口: SPI
电源电压: 5.5 V ~ 18 V
封装/外壳: 32-SOIC(0.295",7.50mm 宽)
供应商设备封装: 32-SOIC
包装: 管件
安装类型: 表面贴装
配用: KIT33689DWBEVB-ND - KIT FOR 33689 SBC WITH LIN
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
33689
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
RXD OUTPUT PIN (LIN PHYSICAL LAYER)
Low-Level Output Voltage
IOUT ≤ 1.5 mA
VOL
0.0
0.9
V
High-Level Output Voltage
IOUT ≤ 250 μA
VOH
3.75
5.25
V
TXD INPUT PIN (LIN PHYSICAL LAYER)
Low-Level Input Voltage
VIL
1.5
V
High-Level Input Voltage
VIH
3.5
V
Input Hysteresis
VINHYS
50
145
300
mV
Pullup Current Source
1.0 V < VTXD < 3.5 V
IPUTXD
-100
-20
μA
LIN PHYSICAL LAYER, TRANSCEIVER
Transceiver Output Voltage
Dominant State, TXD LOW, External Bus Pullup 500
Ω
Recessive State, TXD HIGH, IOUT = 1.0 μA
VLINDOM
VLINREC
VSUP -1.0
1.4
V
Pullup Resistor to VSUP
In Normal Mode and in Sleep and Stop Modes When Not Disabled by
SPI
RPU
20
30
47
k
Ω
Pullup Current Source
In Sleep and Stop Modes When Pullup Disabled by SPI
IPULIN
1.3
μA
Output Current Shutdown Threshold
IOUTSD
50
75
150
mA
Leakage Output Current to GND
VS1 and VS2 Disconnected, VLIN = 18 V
Recessive State, 8.0 V < VSUP < 18 V, 8.0 V < VLIN < 18 V
GND Disconnected, VGND = VSUP, VLIN = -18 V
IBUSLEAK
0.0
-1.0
1.0
3.0
10
20
1.0
μA
mA
LIN PHYSICAL LAYER, RECEIVER
Receiver Input Threshold Voltage
Dominant State, TXD HIGH, RXD LOW
Recessive State, TXD HIGH, RXD HIGH
Center (VBUSDOM -VBUSREC)/ 2
Hysteresis (VBUSDOM -VBUSREC)
VBUSDOM
VBUSREC
VBUSCNT
VBUSHYS
0.0
0.6
0.475
0.5
0.4
1.0
0.525
0.175
VSUP
Bus Wake-Up Threshold
VBUSWU
0.5
VSUP
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V
≤ V
SUP ≤ 18 V, - 40°C ≤ T
A ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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