参数资料
型号: MC33889BDW
厂商: Freescale Semiconductor
文件页数: 32/59页
文件大小: 0K
描述: IC SYSTEM BASE W/CAN 28-SOIC
标准包装: 1
控制器类型: 系统基础芯片
接口: CAN
电源电压: 5.5 V ~ 18 V
电流 - 电源: 45mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
33889
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 17. Simplified State Machine
State Machine (not valid in debug modes)
Power
Down
Reset
Normal Request
Standby
Stop
Normal
Sleep
Reset
counter
(1 ms) expired
S
B
C
po
w
er
up
VDD1 low OR W/D: time
out 350 ms & !Nostop
1
Wa
ke
-u
p
SPI: standby &
W/D
trigger
(note1)
3
SPI
:st
andb
y
S
P
I:n
o
rm
al
SPI: Stop &
CS
low
to
high
transition
SPI:
S
top
&
CS
lo
w t
o
high
transi
tio
n
W
/D:
T
rigge
r
4
2
W/D: timeout OR VDD1 low
Nos
top
&
SP
I:
slee
p
&
CS
low
to
hi
gh
tr
ansit
ion
Nost
op
&
SPI
:
slee
p
&
CS
lo
w
to
high
tra
n
siti
on
W/D: timeout & Nostop & !BATFAIL
1
W/D: timeout OR VDD1 low
1
2
W
/D
: tim
eo
ut O
R
VD
D1
low
(no
te2
)
1
Wake-up
(VDD1 high temperature OR (VDDd1 low > 100 ms & VSUP >BFew)) & Nostop & !BATFAIL
1
2
3
4 denotes priority
State machine description:
“Nostop” means Nostop bit = 1
“! Nostop” means Nostop bit = 0
“BATFAIL” means Batfail bit = 1
“! BATFAIL” means Batfail bit = 0
“VDD1 over temperature” means VDD1 thermal shutdown occurs
“VDD1 low” means VDD1 below reset threshold
“VDD1 low > 100 ms” means VDD1 below reset threshold for more than
100 ms
“W/D: Trigger” means TIM1 register write operation.
VSUP > BFew means VSUP > Battery Fall Early Warning (6.1 V typical)
“W/D: timeout” means TIM1 register not written before W/D timeout period
expired, or W/D written in incorrect time window if window W/D selected
(except stop mode). In normal request mode timeout is 355 ms p2.2
(350 ms p3)ms.
“SPI: Sleep” means SPI write command to MCR register, data sleep
“SPI: Stop” means SPI write command to MCR register, data stop
“SPI: Normal” means SPI write command to MCR register, data normal
“SPI: Standby” means SPI write command to MCR register, data standby
Note 1: these 2 SPI commands must be send in this sequence and
consecutively.
Note 2: if W/D activated
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