参数资料
型号: MC33889BDW
厂商: Freescale Semiconductor
文件页数: 34/59页
文件大小: 0K
描述: IC SYSTEM BASE W/CAN 28-SOIC
标准包装: 1
控制器类型: 系统基础芯片
接口: CAN
电源电压: 5.5 V ~ 18 V
电流 - 电源: 45mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
33889
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 33889 Pin Connections
A functional description of each pin can be found in the Functional pin description section page 24.
Table 2. Pin Definitions
Pin
Pin Name Pin Function
Formal Name
Definition
1
RX
Output
Receiver Data
CAN bus receive data output pin
2
TX
Input
Transmitter Data
CAN bus receive data input pin
3
VDD1
Power
Output
Voltage Regulator One
5.0 V pin is a 2% low drop voltage regulator for to the microcontroller
supply.
4
RST
Output
Reset
This is the device reset output pin whose main function is to reset the
MCU.
5
INT
Output
Interrupt
This output is asserted LOW when an enabled interrupt condition occurs.
6 -9,
20 - 23
GND
Ground
These device ground pins are internally connected to the package lead
frame to provide a 33889-to-PCB thermal path.
10
V2CTRL
Output
Voltage Source 2 Control Output drive source for the V2 regulator connected to the external series
pass transistor.
11
VSUP
Power
Input
Voltage Supply
Supply input pin.
12
HS1
Output
High-Side Output
Output of the internal high-side switch.
13 - 14
L0, L1
Input
Level 0 - 1 Inputs
Inputs from external switches or from logic circuitry.
15
V2
Input
Voltage Regulator Two
5.0 V pin is a low drop voltage regulator dedicated to the peripherals
supply.
16
RTH
Output
RTH
Pin for connection of the bus termination resistor to CANH.
17
RTL
Output
RTL
Pin for connection of the bus termination resistor to CANL.
18
CANH
Output
CAN High
CAN high output pin.
19
CANL
Output
CAN Low
CAN low output pin.
24
SCLK
Input
System Clock
Clock input pin for the Serial Peripheral Interface (SPI).
25
MISO
Output
Master In/Slave Out
SPI data sent to the MCU by the 33889. When CSLOW is HIGH, the pin is
in the high impedance state.
26
MOSI
Input
Master Out/Slave In
SPI data received by the 33889.
WDOG
MISO
SCLK
GND
CANL
CANH
RTL
RTH
V2
CS
MOSI
RX
RST
INT
GND
V2CTRL
VSUP
HS1
L0
L1
TX
VDD1
4
5
6
7
8
9
10
11
12
13
14
2
3
28
25
24
23
22
21
20
19
18
17
16
15
27
26
1
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