参数资料
型号: MC33911G5AC
厂商: Freescale Semiconductor
文件页数: 86/92页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP 32LQFP
标准包装: 250
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
WDERR - Watchdog Error
This read-only bit signals the detection of a missing watchdog
resistor. In this condition the watchdog is using the internal,
lower precision timebase. The Windowing function is
disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
MXx - Analog Multiplexer Input Select
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table 57 .
When disabled or when in Stop or Sleep mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Table 57. Analog Multiplexer Channel Select
WDOFF - Watchdog Off
This read-only bit signals that the watchdog pin connected to
Ground and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
1 = Watchdog is disabled
0 = Watchdog is enabled
WDWO - Watchdog Window Open
MX2
0
0
0
0
1
1
1
MX1
0
0
1
1
0
0
1
MX0
0
1
0
1
0
1
0
Meaning
Disabled
Reserved
Die Temperature Sensor
VSENSE input
L1 input
L2 input
Reserved
This read-only bit signals when the watchdog window is open
for clears. The purpose of this bit is for testing. Should be
ignored in case WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed
Analog Multiplexer Control Register - MUXCR
1 1 1 Reserved
Configuration Register - CFR
This register controls the cyclic sense timing multiplier.
Table 58. Configuration Register - $D
This register controls the analog multiplexer and selects the
divider ration for the Lx input divider.
Table 56. Analog Multiplexer Control Register -$C
C3 C2 C1 C0
Write
Reset
Value
C3
0
0
C2
CYSX8
0
C1
0
0
C0
0
0
Write
LXDS
MX2
MX1
MX0
Reset
Condition
POR, Reset
mode or
ext_reset
POR
POR
POR
Reset
Value
1
0
0
0
CYSX8 - Cyclic Sense Timing x 8.
Reset
Condition
POR
POR, Reset mode or ext_reset
This write-only bit influences the cyclic sense period as
shown in Table 54 .
LXDS - Lx Analog Input Divider Select
This write-only bit selects the resistor divider for the Lx analog
inputs. Voltage is internally clamped to VDD.
1 = Multiplier enabled
0 = None
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)
33911
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
86
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