参数资料
型号: MC33989
厂商: 飞思卡尔半导体(中国)有限公司
元件分类: CAN
英文描述: System Basis Chip with High Speed CAN Transceiver(带高速CAN收发器的系统基片)
中文描述: 系统基础芯片的高速CAN收发器(带高速的CAN收发器的系统基片)
文件页数: 5/32页
文件大小: 676K
代理商: MC33989
MC33989
5
MC33989
Reset Pin (output pin only, supply from Vdd1. Structure switch to gnd with pull up current source)
High Level Output current
Ioh
-300
-250
-150
uA
0<V
out
<0.7Vdd
5.5v<V
sup
<27V
1v<V
sup
<5.5V
V>0.9V
Low Level Output Voltage (I
0
=1.5mA)
Low Level Output Voltage (I
0
=tbd mA)
Reset pull down current
Vol
0
0.9
V
Vol
0
0.9
V
Ipdw
2.3
5
mA
Reset Duration after Vdd1 High
reset-dur
3
3.4
4
ms
Wdogb output pin (Push pull structure)
Low Level Output Voltage (I
0
=1.5mA)
High Level Output Voltage (I
0
=-250uA)
INT Pin( Push pull structure)
Vol
0
0.9
V
1v<V
sup
<27V
Voh
Vdd1-0.9
Vdd1
Low Level Output Voltage (I
0
=1.5mA)
High Level Output Voltage (I
0
=-250uA)
HS1: 150mA High side output pin
Vol
0
0.9
V
Voh
Vdd1-0.9
Vdd1
Rdson at Tj=25°C, and Iout -150mA
Ron25
2
2.5
Ohms
Vsup>9V
Rdson at Ta=125°C, and Iout -150mA
Ron125
4.5
Ohms
Vsup>9V
Rdson at Ta=125°C, and Iout -120mA
Ron125-2
3.5
5.5
Ohms
5.5<Vsup<9V
Output current limitation
Ilim
160
500
mA
Over temperature Shutdown
Ovt
155
190
°C
Leakage current
Ileak
10
uA
Output Clamp Voltage at Iout= -10mA
Vcl
-1.5
-0.3
V
no inductive load drive
capability
L0, L1, L2, L3 inputs
Negative Switching Threshold
Vthn
2
2.5
2.7
2.5
3
3.2
3
3.6
3.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27
Positive Switching Threshold
Vthp
2.7
3
3.5
3.3
4
4.2
3.8
4.6
4.7
V
5.5V<Vsup<6V
6V<Vsup<18V
18V<Vsup<27
Hysteresis
Vhyst
0.6
1.3
V
5.5V<Vsup<27
Input current
Iin
-10
10
uA
-0.2V < Vin < 40V
Wake up Filter Time
Twuf
8
20
38
us
DIGITAL INTERFACE TIMING
SPI operation frequency
Freq
0.25
4
MHz
SCLK Clock Period
t
pCLK
t
wSCLKH
t
wSCLKL
250
N/A
ns
SCLK Clock High Time
125
N/A
ns
SCLK Clock Low Time
125
N/A
ns
Falling Edge of CS to Rising
Edge of SCLK
t
lead
100
N/A
ns
Falling Edge of SCLK to Rising Edge of
CS
t
lag
100
N/A
ns
MOSI to Falling Edge of SCLK
t
SISU
t
SIH
t
rSO
t
fSO
40
N/A
ns
Falling Edge of SCLK to MOSI
40
N/A
ns
MISO Rise Time (CL = 220pF)
25
50
ns
MISO Fall Time (CL = 220pF)
25
50
ns
Time from Falling or Rising Edges of CS to:
- MISO Low Impedance
- MISO High Impedance
t
SOEN
t
SODIS
50
50
ns
Time from Rising Edge of SCLK to MISO
Data Valid
t
valid
50
ns
0.2 V1=<MISO>=0.8V1,
C
L
=200pF
(V
sup
From 5.5V to 18V and Tamb -40°C to 125°C)
For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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