参数资料
型号: MC33989
厂商: 飞思卡尔半导体(中国)有限公司
元件分类: CAN
英文描述: System Basis Chip with High Speed CAN Transceiver(带高速CAN收发器的系统基片)
中文描述: 系统基础芯片的高速CAN收发器(带高速的CAN收发器的系统基片)
文件页数: 6/32页
文件大小: 676K
代理商: MC33989
MC33989
6
MC33989
STATE MACHINE TIMING
note 1: delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn on” or “Turn off” of HS1 or V2.
Delay between CSB low to high transis-
tion (at end of SPI stop command) and
Stop mode activation
Tcsb-stop
18
34
us
Guaranteed by design
detected by V2 off
Interrupt low level duration
Tint
7
10
13
us
SBC in stop mode
Internal oscillator frequency
Osc-f1
100
kHz
All modes except Sleep
and Stop, guaranted by
design
Internal low power oscillator frequency
Osc-f2
100
kHz
Sleep and Stop modes,
guaranted by design
Watchdog period 1
Wd1
8.58
9.75
10.92
ms
Normal and standby modes
Watchdog period 2
Wd2
39.6
45
50.4
ms
Normal and standby modes
Watchdog period 3
Wd3
88
100
112
ms
Normal and standby modes
Watchdog period 4
Wd4
308
350
392
ms
Normal and standby modes
Watchdog period accuracy
F1acc
-12
12
%
Normal and standby modes
Normal request mode timeout
NRtout
308
350
392
ms
Normal request mode
Watchdog period 1 - stop
Wd1stop
6.82
9.75
12.7
ms
Stop mode
Watchdog period 2- stop
Wd2stop
31.5
45
58.5
ms
Stop mode
Watchdog period 3 - stop
Wd3stop
70
100
130
ms
Stop mode
Watchdog period 4 - stop
Wd4stop
245
350
455
ms
Stop mode
Stop mode watchdog period accuracy
F2acc
-30
30
%
Stop mode
Cyclic sense/FWU timing 1
CSFWU1
3.22
4.6
5.98
ms
Sleep and stop modes
Cyclic sense/FWU timing 2
CSFWU2
6.47
9.25
12
ms
Sleep and stop modes
Cyclic sense/FWU timing 3
CSFWU3
12.9
18.5
24
ms
Sleep and stop modes
Cyclic sense/FWU timing 4
CSFWU4
25.9
37
48.1
ms
Sleep and stop modes
Cyclic sense/FWU timing 5
CSFWU5
51.8
74
96.2
ms
Sleep and stop modes
Cyclic sense/FWU timing 6
CSFWU6
66.8
95.5
124
ms
Sleep and stop modes
Cyclic sense/FWU timing 7
CSFWU7
134
191
248
ms
Sleep and stop modes
Cyclic sense/FWU timing 8
CSFWU8
271
388
504
ms
Sleep and stop modes
Cyclic sense On time
Ton
200
350
500
us
in sleep and stop modes
threshold and condition to
be added
Cyclic sense/FWU timing accuracy
Tacc
-30
+30
%
in sleep and stop mode
Delay between SPI command and HS1
turn on (note 1)
Ts-HSon
22
us
Normal or standby mode
Vsup>9V
Delay between SPI command and HS1
turn off (note 1)
Ts-HSoff
22
us
Normal or standby mode
Vsup>9V
Delay between SPI and V2 turn on
(note 1)
Ts-V2on
9
22
us
Standby mode
Delay between SPI and V2 turn off
(note 1)
Ts-V2off
9
22
us
Normal modes
Delay between Normal Request and Nor-
mal mode, after W/D trigger command
Ts-NR2N
15
35
70
us
Normal request mode
Delay between SPI and “CAN normal
mode”
Ts-CANn
10
us
SBC Normal mode
guaranteed by design
Delay between SPI and “CAN sleep
mode”
Ts-CANs
10
us
SBC Normal mode
guaranteed by design
(V
sup
From 5.5V to 18V and Tamb -40°C to 125°C)
For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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