参数资料
型号: MC34827A1EPR2
厂商: Freescale Semiconductor
文件页数: 22/57页
文件大小: 0K
描述: IC USB POWER MANAGER 20-QFN
标准包装: 1
应用: OR 控制器,UART/USB 数据,音频管理
电流 - 电源: 9µA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-UFQFN 裸露焊盘
供应商设备封装: 20-QFN 裸露焊盘(3x3)
包装: 标准包装
其它名称: MC34827A1EPR2DKR
FUNCTIONAL DEVICE OPERATION
OPERATION AFTER IDENTIFICATION
V BUS
PSTI_EN
SW1
SW2
SW3
SW4
DP/DM_Short
DP/DM_reverse_Short
VBUS_DET_END
t 0
t 1
t 2
t 3
t 4
t 5
t 6
t D
t D 1
Figure 17. Operating Waveforms for the PSTI Circuit
OPERATION AFTER IDENTIFICATION
The identification process is started when VDD is above
POR and the accessory attachment is detected. After the
identification process is finished, the operation of the 34827
is determined together by the type of accessory, that is JIG
cable or non-JIG cable, the status of power supplies,
including the VBUS, VDD and VDDIO, and the Control
register values.
If VBUS is powered up and VDD and VDDIO are low, the
identification flow is not started. The 34827 is in the VBUS
Power mode. The power MOSFET is on and ISET outputs
high impedance. The JIG pin outputs high impedance, and
the BOOT pin outputs logic low voltage for all accessories.
When VDD increases above POR but VDDIO is still low,
the identification flow is started. But the interrupt mask control
bit INT_MASK in Control register is in reset state (‘1’) to mask
type of accessory is attached. This condition happens when
the cell phone is not powered up yet. In this condition, if the
accessory is found to be a JIG cable, the JIG pin outputs low
impedance to enable the PMIC in the cell phone. Then
VDDIO rises. Once the VDDIO rises to high, the BOOT pin
will output the correct logic voltage and the UART or the USB
switches will be turned on according to the type of JIG cable.
When the VDDIO is started up, the INT_MASK bit is still in
reset state ‘1’, and the INTB output stays low. If the accessory
is not a JIG cable, when the VDD and VDDIO are both
powered up, the signal switches remains off until the
INT_MASK is written to ‘0’ by I 2 C.
The behaviors of INTB and signal switches during such
transition and other important control functions are described
below in detail.
all interrupt outputs. All signal switches are off no matter what
CONTROL FUNCTIONS
The 34827 contains registers which hold control and
status information. The register map and the description of
each register can be found in Register Map section. The
details about some important control bits are described as
follows.
INTERRUPT MASK (INT_MASK)
The INT_MASK bit masks all interrupt outputs to the host.
When the INT_MASK bit is ‘1’, the INTB output is forced to
low, and the corresponding interrupt bit can be still set when
an interrupt event happens, but the host should not read the
interrupt registers when INT_MASK = 1. When INT_MASK bit
is set to ‘0’, the INTB output is allowed to send an interrupt, if
any, to the host after a delay as shown in Figure 18 . The
delay is a WAIT time programmed by the Switching Wait bits
in Timing Set 2 register. During the delay time, the INTB
outputs a high voltage, and the host is not allowed to read the
interrupt registers.
Figure 18 illustrates the switching behavior when the
INT_MASK is set to ‘0’. Figure (A) shows the case that no
interrupt bit is already set. In this case, the INTB outputs high
when INT_MASK bit is set to zero. Figure (B) shows the case
that an interrupt bit is already set due to attachment of an
accessory and WAIT = 1 when the first delay time expires. In
this case, INTB outputs high voltage during the first delay
time and then outputs low voltage when the delay time
expires. Once the INTB outputs low voltage after the delay
time, the 34827 waits for a second WAIT time before turning
on the signal switches. The baseband should read the
interrupt registers via the I 2 C, and since all the interrupt bits
are of R/C type, the interrupt bits will be cleared after being
read and then the INTB output returns to high. Figure (C)
MC34827
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
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