参数资料
型号: MC34911G5ACR2
厂商: Freescale Semiconductor
文件页数: 74/92页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP LIN 32-LQFP
标准包装: 2,000
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 带卷 (TR)
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RST Wake-up
While in Stop mode, the 33911 can wake-up when the RST
pin is held low long enough to pass the internal glitch filter.
Then, it will change to Normal Request or Normal modes
depending on the WDCONF pin configuration. The RST
wake-up does not generate an interrupt and is not reported
via the SPI.
From Stop mode, the following wake-up events can be
configured:
? Wake-up from Lx inputs without cyclic sense
? Cyclic sense wake-up inputs
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WD TIMING X 50%
WINDOW OPEN
FOR WATCHDOG
CLEAR
WD TIMING X 50%
? Force wake-up
? CS wake-up
? LIN wake-up
? RST wake-up
From Sleep mode, the following wake-up events can be
configured:
? Wake-up from Lx inputs without cyclic sense
? Cyclic sense wake-up inputs
? Force wake-up
? LIN wake-up
WINDOW WATCHDOG
The 33911 includes a configurable window watchdog which
is active in Normal mode. The watchdog can be configured by
an external resistor connected to the WDCONF pin. The
resistor is used to achieve higher precision in the timebase
used for the watchdog.
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR).
During the first half of the SPI timeout, watchdog clears are
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33911 will reset the MCU, in the
same way as when the watchdog overflows.
WD PERIOD (t PWD )
WD TIMING SELECTED BY REGISTER
ON WDCONF PIN
Figure 39. Window Watchdog Operation
To disable the watchdog function in Normal mode, the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset mode.
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the WDSR.
The watchdog timebase can be further divided by a prescaler
which can be configured by the Timing Control Register
(TIMCR). During Normal Request mode, the window
watchdog is not active but there is a 150 ms (typ.) timeout for
leaving the Normal Request mode. In case of a timeout, the
33911 will enter into Reset mode, resetting the
microcontroller before entering again into Normal Request
mode.
HIGH SIDE OUTPUT PIN HS1
This output is one high side driver intended to drive small
resistive loads or LEDs incorporating the following features:
? PWM capability (software maskable)
? Open-load detection
? Current limitation
? Over-temperature shutdown (with maskable interrupt)
? High-voltage shutdown (software maskable)
? Cyclic sense
The high side switch is controlled by the HS1 bit in the High
Side Control Register (HSCR).
PWM Capability (direct access)
The high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If the HS1 bit and PWMHS1 is set in the HSCR, then the HS1
driver is turned on if the PWMIN pin is high, and turned off if
the PWMIN pin is low.
33911
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
74
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