参数资料
型号: MC34911G5ACR2
厂商: Freescale Semiconductor
文件页数: 85/92页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP LIN 32-LQFP
标准包装: 2,000
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 带卷 (TR)
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Timing Control Register - TIMCR
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
This option is only active if the high side switch is enabled
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in Table 54 .
Table 54. Cyclic Sense Interval
CYSX8 (127) CYST2 CYST1 CYST0 Interval
Table 52. Timing Control Register - $A
X
0
0
0
No cyclic sense
Write
C3
CS/WD
C2
WD2
CYST2
C1
WD1
CYST1
C0
WD0
CYST0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
20ms
40ms
60ms
80ms
Reset
Value
Reset
Condition
-
-
0
0
POR
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
100ms
120ms
140ms
160ms
CS/WD - Cyclic Sense or Watchdog prescaler select.
This write-only bit selects which prescaler is being written to,
the Cyclic Sense prescaler or the watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = watchdog Prescaler select
WDx - Watchdog Prescaler
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
320ms
480ms
640ms
800ms
960ms
1120ms
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 53 . This configuration is valid only if
windowing watchdog is active.
Notes
127. bit CYSX8 is located in Configuration Register (CFR)
Watchdog Status Register - WDSR
Table 53. Watchdog Prescaler
WD2 WD1 WD0
Prescaler Divider
This register returns the watchdog status information and is
also returned when writing to the TIMCR.
0
0
0
1
Table 55. Watchdog Status Register - $A/$B
0
0
1
2
S3
S2
S1
S0
0
1
0
4
Read
WDTO
WDERR
WDOFF
WDWO
0
1
1
6
1
0
0
8
WDTO - Watchdog Timeout
1 0 1 10
1 1 0 12
1 1 1 14
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up cyclic
sensing together with the bit CYSX8 in the Configuration
Register (CFR) (see Configuration Register - CFR ).
This read-only bit signals the last reset was caused by either
a watchdog timeout or by an attempt to clear the watchdog
within the window closed.
Any access to this register or the TIMCR will clear the WDTO
bit.
1 = Last reset caused by watchdog timeout
0 = None
33911
Analog Integrated Circuit Device Data ?
85
Freescale Semiconductor
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