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| 型号： | MC3510 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | 8位微控制器 |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | ECONOLINE：RSZ / P - 1kVDC 2kVDC隔离UL94V - 0封装材料所需的散热片，无外置。组件所需的环形磁ContinuousShort电路保护（/ P的后缀） |
| 文件页数： | 45/75页 |
| 文件大小： | 1023K |
| 代理商： | MC3510 |
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MC3510 Technical Specifications
45
6.3
8-bit Host Interface (IOPIL8)
This design implements a parallel interface with a host processor utilizing an 8-bit data bus. An
understanding of the underlying operation of the design is only necessary if the designer intends to
make modifications. In most cases this design can be implemented without changes. The following
notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The
timing for the host to I/O chip communication can be found in section 4.4 and the timing for the
CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side
signals. The paragraph title identifies the key schematic(s) being described in the text.
IOPIL8 3
The host interface for IOPIL8 is shown in sheet IOPIL8 3. The incoming data HD[7:0] is latched in
the transparent latches when ~HG1 goes high. This would be a write from the host to the CP. The
latched data HI[7:0] goes to IOPIL8 1 and IOPIL8 5. Data from the interface to the host, HO[7:0]
is enabled onto the host bus, HD[7:0], by HOES1. The output latches, which present the data
during a host read, are always transparent because GOUT
is connected to VDD. The latched I/O is
an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD
or FPGA does not have this feature. HD[15:8] are tri-stated outputs because Actel grounds unused
I/O pins and this would interfere with using existing PMD test equipment. These reserved I/O's can
be ommitted in a different implementation with an 8 bit bus.
IOPIL8 1
The control for the host interface starts on IOPIL8 1. HOES1 is the AND of ~HSEL and ~HRD,
and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to
the host to allow asynchronous communication between the host and the CP. The host must wait
until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in
the host status register. The host status register may be read at any time to determine the state of
HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and
HA0 are the buffered inputs of the host control signals.
HOST INTERFACE/IOPIL8 5
Data from the host HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE
by ~EN1 and ~EN2. All transfers are 16 bits and take two writes or reads on the 8-bit bus. These
registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to this
register.
This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which
are multiplexer based but if the configuration of the logic device used demands it, separate registers
could be used for the host and CP data. The schematic for this register is shown as DFME8. Only
commands and checksums are written to registers REG1 and REG2 while data is written and read
from the set of data registers, DATREG shown on IOPIL8 5. These 3 data registers buffer data sent
to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1
and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL8 5, where they are multiplexed with the other data
registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] -
the output of the host status registers REG3 and REG4. This four input mux, MUX4X8, also
muxes the 16 bit data onto the 8-bit bus. As previously mentioned HRDY becomes HST15 so it can
be read by the host. The rest of the status register is written by the CP to provide information to the
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