参数资料
| 型号： | MC3PHACVPE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR CONTROLLER 28-DIP |
| 标准包装： | 13 |
| 应用： | AC 电机控制器，3 相 |
| 输出数： | 1 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 28-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 28-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 808 (CN2011-ZH PDF) |
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Pin Descriptions
Pin Descriptions
Table 2 is a pin-by-pin functional description of the MC3PHAC. The pin numbers in the table refer to the
28-pin packages (see Figure 2 ).
Table 2. MC3PHAC Pin Descriptions (Sheet 1 of 2)
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
V REF
RESET
V DDA
V SSA
OSC2
OSC1
PLLCAP
PWMPOL_BASEFREQ
PWM_U_TOP
PWM_U_BOT
PWM_V_TOP
PWM_V_BOT
PWM_W_TOP
PWM_W_BOT
FAULTIN
PWMFREQ_RxD
Pin Function
Reference voltage input for the on-chip ADC. For best signal-to-noise
performance, this pin should be tied to V DDA (analog).
A logic 0 on this pin forces the MC3PHAC to its initial startup state. All
PWM outputs are placed in a high-impedance mode. Reset is a
bidirectional pin, allowing a reset of the entire system. It is driven low
when an internal reset source is asserted (for example, loss of clock or
low V DD ).
Provides power for the analog portions of the MC3PHAC, which include
the internal clock generation circuit (PLL) and the ADC
Returns power for the analog portions of the MC3PHAC, which include
the internal clock generation circuit (PLL) and the ADC
Oscillator output used as part of a crystal or ceramic resonator clock
circuit. (1)
Oscillator input used as part of a crystal or ceramic resonator clock
circuit. Can also accept a signal from an external canned oscillator. (1)
A capacitor from this pin to ground affects the stability and reaction time
of the PLL clock circuit. Smaller values result in faster tracking of the
reference frequency. Larger values result in better stability. A value of
0.1 μ F is typical.
Input which is sampled at specific moments during initialization to
determine the PWM polarity and the base frequency (50 or 60 Hz)
PWM output signal for the top transistor driving motor phase U
PWM output signal for the bottom transistor driving motor phase U
PWM output signal for the top transistor driving motor phase V
PWM output signal for the bottom transistor driving motor phase V
PWM output signal for the top transistor driving motor phase W
PWM output signal for the bottom transistor driving motor phase W
A logic high on this input will immediately disable the PWM outputs. A
retry timeout interval will be initiated once this pin returns to a logic low
state.
In standalone mode, this pin is an output that drives low to indicate the
parameter mux input pin is reading an analog voltage to specify the
desired PWM frequency. In PC master software mode, this pin is an
input which receives UART serial data.
MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2
6
Freescale Semiconductor
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