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参数资料
| 型号： | MC44461 |
| 厂商： | Motorola, Inc. |
| 英文描述： | PICTURE-IN-PICTURE (PIP) CONTROLLER |
| 中文描述： | 子母画中画（PIP）控制器 |
| 文件页数： | 12/16页 |
| 文件大小： | 314K |
| 代理商： | MC44461 |
MC44461
12
MOTOROLA ANALOG IC DEVICE DATA
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I2C REGISTER TABLE
address
Values
45h
1Ah
07h
02h
20h
01h
34h
24h
20h
20h
02h
–
00h
00h
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01h
02h
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03h
04h
05h
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06h
07h
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08h
09h
0Ah
0Bh
0Ch
D7
–
–
MHP0
PSEL0
–
–
–
–
–
–
D6
D5
D4
D3
D2
D1
D0
–
–
MVP0
MSEL0
–
–
–
–
–
–
–
–
–
–
–
PSI90
–
XPS5
YPS5
C5
T5
–
VFON
–
–
STIL0
PBL0
XPS4
YPS4
C4
T4
–
–
–
PSD3
–
–
–
–
XPS3
YPS3
C3
T3
–
PSD2
BC2
ITM2
–
–
XPS2
YPS2
C2
T2
YDL2
–
–
PSD1
BC1
ITM1
XPS1
YPS1
C1
T1
YDL1
PSD0
BC0
ITM0
–
PON0
XPS0
YPS0
C0
T0
YDL0
–
–
–
–
–
–
–
–
–
–
–
–
CIRCUIT DESCRIPTION
The MC44461 Picture–in–Picture (PIP) controller is
composed of an analog section, logic section and an
8192 x 8–bit DRAM array. A block diagram showing details of
all of these sections is shown in the Representative Block
Diagram.
The analog section includes an Input Switch, Sync
Processor, Filters, PLLs, NTSC Decoder, ADC, DACs, NTSC
Encoder and Output Switch. All necessary controls are
provided by registers in the logic section. These registers are
set by external control through the I2C Bus.
In operation, the MC44461 overlays a single PIP on the
main video in either a 1/9th or 1/16th size. In 1/9th, the PIP is
152 samples (114 Y, 19 V, 19 U) by 70 lines and occupies
8094 bytes of the 8192 byte DRAM. The 1/16 size is 112
samples (84 Y, 14 V, 14 U) by 52 lines and occupies 4452
bytes of the DRAM. An extra line of data is stored for each
PIP size to allow for interlace disorder correction. The 6:1:1
samples are formatted by the logic section as follows in order
to efficiently utilize memory:
Byte 1: Y0(5:0), V(1:0)
Byte 2: Y1(5:0), V(3:2)
Byte 3: Y2(5:0), V(5:4)
Byte 4: Y3(5:0), U(1:0)
Byte 5: Y4(5:0), U(3:2)
Byte 6: Y5(5:0), U(5:4)
Refer to the block diagram. Both the video inputs are
applied to an input switch which is controlled by the I2C bus
interface. Either of the inputs is applied to the PIP processing
circuitry and either to the main video signal path of the output
switch. The signal applied to the PIP processor also provides
the vertical sync reference to the PIP processor.
The PIP output from the switch is applied to a 1.0 MHz
cutoff low pass GmC biquad filter to extract the luminance
signal and a similar bandpass filter to pass chroma to the
decoder section. These filters are tracked to a master GmC
cell using subcarrier as a reference. A single–ended
transconductance stage with relatively large signal handling
ability (>2.5 Vpp @ 4.5 V VCC) is used to avoid potential
noise problems.
Figure 5. NTSC Decoder
Color
Killer
In
90
°
ACC
Switching
PLL
Filter
XVCO/
Divide
Mult 1
Mult 2
BG
H
U
V
0
°
The NTSC Decoder (Figure 5) consists of two multipliers,
a voltage controlled 4 X S/C crystal oscillator/divider,
Automatic Color Control (ACC) block, Color Kill circuit and
necessary switching. During Burst Gate time, the ACC block
in the NTSC Decoder is calibrated with respect to burst
magnitude by applying the output of multiplier 1 to the
reference input of the ACC block. The result is U and V
outputs which are 0.6 V
±
0.5 dB for burst amplitudes varying
from –12 dB to 3.0 dB. The second multiplier serves as a
phase detector during color burst to match the 90 degree
output from the XVCO to the 180 degree color burst and feed
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相关代理商/技术参数 |
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| MC44461B | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462B | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44463 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44463B | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER |
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