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参数资料
| 型号： | MC44461 |
| 厂商： | Motorola, Inc. |
| 英文描述： | PICTURE-IN-PICTURE (PIP) CONTROLLER |
| 中文描述： | 子母画中画（PIP）控制器 |
| 文件页数： | 13/16页 |
| 文件大小： | 314K |
| 代理商： | MC44461 |
MC44461
13
MOTOROLA ANALOG IC DEVICE DATA
a correction current to the PLL filter. The phase is correct
when the two signals are 90 degrees out of phase.
During the H drive time, the output of the multipliers is fed
to the YUV clamp, filtered to 200 KHz and input along with the
Y signal to the multiplexer.
The YUV samples are fed through a multiplexer to a single
six bit A/D converter. The A/D is a flash type architecture and
is capable of digitizing at a 20 MHz sample rate. It is
comprised of an internal bandgap source voltage reference,
a 64 tap resistor ladder comparator array, a binary encoder
and output latches. Once the multiplexer has switched,
sufficient time is provided to allow the A/D converter to settle
before the reading is latched. The encoder code is
determined from the values of any comparators which are not
metastable.
The multiplexer and A/D converter receive and convert the
YUV data at a 4FSC/3 rate for a 1/9th size picture or FSC for
a 1/16th size picture. The samples are taken in the following
way to simplify the control logic:
Y,V,Y,U,Y,V,Y,U
To provide a 6:1:1 format, one of three U and V samples is
saved to memory giving a luminance sample rate of 2FSC/3
for a 1/9th picture and FSC/2 for a 1/16 picture. In the vertical
direction, one line of every 3 (1/9th picture) or 4 (1/16th
picture) are saved. In order to avoid objectionable artifacts, a
piece–wise vertical filter is used to take a weighted average
on the luminance samples. For three lines (1/9th size) the
weight is 1/4 + 1/2 + 1/4 and for four lines (1/16 size) it is
1/4 + 1/4 + 1/4 + 1/4. This filter also delays the luma samples
correcting for the longer chroma signal path through the
decoder.
Finally the logic incorporates a field generator to
determine the current field in order to correct interlace
disorders arising from a single field memory.
A separate process runs in the logic section to create the
PIP window on the main picture. Control signals are
generated and sent to the memory controller to read data
from the field memory. Data from the eight bit memory are
then de–multiplexed into a six bit YUV format, borders are
added, blanking is generated for the video clamps and sent to
the Y, U and V DACs. Since the PIP display is based on a
data clock, it is important to minimize the main display clock
skew on a line by line basis. Skew is minimized in the
MC44461 by reclocking the display timebase to the nearest
rising or falling edge of a 16FSC clock. This produces a
maximum line to line skew of approximately 8.0 ns which is
not perceptible to the viewer. The PIP write logic also
incorporates a field generator for use by the memory
controller for interlace disorder correction. Interlace disorder
can occur when the line order of the two fields of the PIP
image is swapped due to a mismatch with the main picture
field or due to an incomplete field being displayed from
memory. The main and PIP field generators, along with
monitoring, when the PIP read address passes the PIP write
address, allows the read address to the memory to be
modified to correct for interlace disorder.
The read logic can provide various border colors: black,
75% white (light gray), 50% white (medium gray), red, green,
blue or transparent (no border). In a system without an
adaptive comb filter, borders which contain no chroma give
the best results. Also built into the read logic is a PIP fill mode
which allows the PIP window to be filled with either a solid
green, blue or red color as an aid in aligning the PIP analog
color circuitry.
Because the DAC output video will be referenced during
back porch time, the read processor zeroes the luminance
value and sets the bipolar U and V values to mid–range
during periods outside the PIP window to ensure clamping at
correct levels. Since the PIP window is positioned relative to
the main picture’s vertical and horizontal sync, a safety
feature turns off the window if the window encroaches upon
the sync period, thus preventing erroneous clamping.
The Y, U and V DACs are all three of the same design. A
binary weighted current source is used, split into two, three
bit levels. In the three most significant bits, the current
sources are cascaded to improve the matching to the three
least significant current sources. Analog transmission gates,
switched by the bi–phase outputs of the data latches, feed
the binary currents to the single ended current mirror. The
output current is subsequently clamped and filtered for
processing buy the NTSC Encoder.
The outputs of the U and V DACS are buffered and burst
flag pulses added to both signals. The U burst flag is fixed to
generate a –180
°
color burst at the modulator output. The V
burst flag is variable under the control of an internal register
set through the I2C bus to provide a variable tint. Saturation is
controlled by varying a register which sets the reference
voltage to the U and V DACs. This is also under I2C bus
control. By oversampling the U and V DACs, it was possible
to use identical post–DAC filtering for Y, U and V, thereby
reducing the delay inequalities between Y and UV and also
simplifying the design. After filtering, the U and V signals are
clamped to an internal reference voltage during horizontal
blanking periods and fed to the U and V modulators. In the
NTSC Decoder, the Y, U and V signals were scaled to use the
entire A/D range. Gain through the NTSC Encoder is set to
properly match these amplitudes.
The phase of the re–encoded chrominance must match
that of the incoming main video signal at the input to the PIP
switch, so a separate first order PLL is placed within the loop
of the main video signal burst PLL. The first order PLL
compares the phase of the main burst with that of the
encoded burst and moves the oscillator phase so that they
match. A special phase shift circuit allowing a continuous
range of 180
°
was developed to do this.
The amplitude of the re–encoded chrominance signal
must also match that of the main video signal. To do this, a
synchronous amplitude comparator looks at both burst
signals and adjusts the chrominance amplitude in the
modulator section of the NTSC encoder. The Y signal from
the YDAC is compared to the main video signal at black level
during back porch time and clamped to this same black level
voltage. The PIP chrominance and luminance are then
added together and fed to the PIP output switch through a
buffered output.
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| MC44462B | Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
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| MC44463B | RV Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 09V; Power: 2W; High Isolation 2W Converter; Approved for Medical Applications; EN and UL Safety Certificates; 6kVDC Isolation; Skinny DIP24 Package; Optional Continuous Short Circuit Protected; Fully Encapsulated; Very Low Isolation Capacitance |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC44461B | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462B | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44463 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44463B | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER |
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