参数资料
型号: MC56F8145VFG
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封装: PLASTIC, LQFP-128
文件页数: 28/172页
文件大小: 871K
代理商: MC56F8145VFG
Flash Access Blocking Mechanisms
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
123
Preliminary
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to
control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control
the period of the clock used for timed events in the FM erase algorithm. This register must be set with
appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300
Peripheral User Manual for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides
down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the
PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV
must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD
Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific
equations for calculating the correct values.
Figure 7-1 JTAG to FM Connection for Lockout Recovery
Two examples of FM_CLKDIV calculations follow.
SYS_CLK
JTAG
FMCLKD
DIVIDER
7
2
FM_CLKDIV
FM_ERASE
Flash Memory
clock
input
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