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参数资料
型号： MC56F8145VFG
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 数字信号处理
英文描述： 4-BIT, 120 MHz, OTHER DSP, PQFP128
封装： PLASTIC, LQFP-128
文件页数： 5/172页
文件大小： 871K
代理商： MC56F8145VFG
56F8345 Technical Data, Rev. 17
102
Freescale Semiconductor
Preliminary
5.6.30
ITCN Control Register (ICTL)
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1
Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2
Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.6.30.3
Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.6.30.4
Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5
Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
Base + $1D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
INT
IPIC
VAB
INT_DIS
1
IRQB STATE
IRQA STATE
IRQB
EDG
IRQA
EDG
Write
RESET
0
10
000
00
0
1
0
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