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| 型号： | MC68332GVFV20 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144 |
| 文件页数： | 62/109页 |
| 文件大小： | 787K |
| 代理商： | MC68332GVFV20 |
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MOTOROLA
MC68332
56
MC68332TS/D
5.2.3 Queued Output Match (QOM)
QOM can generate single or multiple output match events from a table of offsets in parameter RAM.
Loop modes allow complex pulse trains to be generated once, a specified number of times, or continu-
ously. The function can be triggered by a link from another TPU channel. In addition, the reference time
for the sequence of matches can be obtained from another channel. QOM can generate pulse-width
modulated waveforms, including waveforms with high times of 0% or 100%. QOM also allows a TPU
channel to be used as a discrete output pin.
5.2.4 Programmable Time Accumulator (PTA)
PTA accumulates a 32-bit sum of the total high time, low time, or period of an input signal over a pro-
grammable number of periods or pulses. The accumulation can start on a rising or falling edge. After
the specified number of periods or pulses, the PTA generates an interrupt request and optionally gen-
erates links to other channels.
From 1 to 255 period measurements can be made and summed with the previous measurement(s) be-
fore the TPU interrupts the CPU, providing instantaneous or average frequency measurement capabil-
ity, and the latest complete accumulation (over the programmed number of periods).
5.2.5 Multichannel Pulse Width Modulation (MCPWM)
MCPWM generates pulse-width modulated outputs with full 0% to 100% duty cycle range independent
of other TPU activity. This capability requires two TPU channels plus an external gate for one PWM
channel. (A simple one-channel PWM capability is supported by the QOM function.)
Multiple PWMs generated by MCPWM have two types of high time alignment: edge aligned and center
aligned. Edge aligned mode uses n + 1 TPU channels for n PWMs; center aligned mode uses 2n + 1
channels. Center aligned mode allows a user defined ‘dead time’ to be specified so that two PWMs can
be used to drive an H-bridge without destructive current spikes. This feature is important for motor con-
trol applications.
5.2.6 Fast Quadrature Decode (FQD)
FQD is a position feedback function for motor control. It decodes the two signals from a slotted encoder
to provide the CPU with a 16-bit free running position counter. FQD incorporates a “speed switch” which
disables one of the channels at high speed, allowing faster signals to be decoded. A time stamp is pro-
vided on every counter update to allow position interpolation and better velocity determination at low
speed or when low resolution encoders are used. The third index channel provided by some encoders
is handled by the ICTC function.
5.2.7 Universal Asynchronous Receiver/Transmitter (UART)
The UART function uses one or two TPU channels to provide asynchronous communications. Data
word length is programmable from 1 to 14 bits. The function supports detection or generation of even,
odd, and no parity. Baud rate is freely programmable and can be higher than 100 Kbaud. Eight bidirec-
tional UART channels running in excess of 9600 baud could be implemented on the TPU.
5.2.8 Brushless Motor Commutation (COMM)
This function generates the phase commutation signals for a variety of brushless motors, including
three-phase brushless direct current. It derives the commutation state directly from the position decod-
ed in FQD, thus eliminating the need for hall effect sensors.
The state sequence is implemented as a user-configurable state machine, thus providing a flexible ap-
proach with other general applications. A CPU offset parameter is provided to allow all the switching
angles to be advanced or retarded on the fly by the CPU. This feature is useful for torque maintenance
at high speeds.
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