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| 型号： | MC68334GEH16 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 36/76页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 16MHZ 132-PQFP |
| 标准包装： | 36 |
| 系列： | M683xx |
| 核心处理器： | CPU32 |
| 芯体尺寸： | 32-位 |
| 速度： | 16MHz |
| 连通性： | EBI/EMI，UART/USART |
| 输入/输出数： | 47 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 数据转换器： | A/D 8x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 132-BQFP 缓冲式 |
| 包装： | 托盘 |
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MC68334
MC68334TS/D REV. 1
41
%1111. In order to implement an arbitration scheme, each module that can initiate an interrupt service
request must be assigned a unique, non-zero IARB field value during system initialization. Arbitration
priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an interrupt service
request from a source that has an IARB field value of %0000, a spurious interrupt exception is pro-
cessed.
WARNING
Do not assign the same arbitration priority to more than one module. When two or
more IARB fields have the same nonzero value, the CPU32 interprets multiple vec-
tor numbers at the same time, with unpredictable consequences.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the
reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same priority, it always takes
place, even when a single source is requesting service. This is important for two reasons: the EBI does
not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention,
and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error.
When arbitration is complete, the module with the highest arbitration priority must terminate the bus
cycle. Internal modules place an interrupt vector number on the data bus and generate appropriate in-
ternal cycle termination signals. In the case of an external interrupt request, after the interrupt acknowl-
edge cycle is transferred to the external bus, the appropriate external device must decode the mask
value and respond with a vector number, then generate data and size acknowledge (DSACK) termina-
tion signals, or it must assert the autovector (AVEC) request signal. If the device does not respond in
time, the EBI bus monitor asserts the bus error signal BERR, and a spurious interrupt exception is tak-
en.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in response to interrupt
requests from external devices. Chip-select address match logic functions only after the EBI transfers
an interrupt acknowledge cycle to the external bus following IARB contention. If a module makes an
interrupt request of a certain priority, and the appropriate chip-select registers are programmed to gen-
erate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chip-
select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a
vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PICR) determines
PIT priority level. A PIRQ value of %000 means that PIT interrupts are inactive. By hardware conven-
tion, when the CPU32 receives simultaneous interrupt requests of the same level from more than one
SIM source (including external devices), the periodic interrupt timer is given the highest priority, followed
by the IRQ pins. Refer to 3.2.7 Periodic Interrupt Timer for more information.
3.8.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. The processor state is stacked. The S bit in the status register is set, establishing supervisor
access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
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