MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
5-53
When arbitration is complete, the module with both the highest asserted interrupt level
and the highest arbitration priority must terminate the bus cycle. Internal modules
place an interrupt vector number on the data bus and generate appropriate internal
cycle termination signals. In the case of an external interrupt request, after the interrupt
acknowledge cycle is transferred to the external bus, the appropriate external device
must respond with a vector number, then generate data and size acknowledge
(DSACK) termination signals, or it must assert the autovector (AVEC) request signal.
If the device does not respond in time, the SIM bus monitor, if enabled, asserts the bus
error signal (BERR), and a spurious interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-
logic functions only after the EBI transfers an interrupt acknowledge cycle to the exter-
nal bus following IARB contention. If an internal module makes an interrupt request of
a certain priority, and the appropriate chip-select registers are programmed to gener-
ate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that
priority level, chip-select logic does not respond to the interrupt acknowledge cycle,
and the internal module supplies a vector number and generates internal cycle termi-
nation signals.
For periodic timer interrupts, the PIRQ[2:0] field in the periodic interrupt control register
(PICR) determines PIT priority level. A PIRQ[2:0] value of %000 means that PIT inter-
rupts are inactive. By hardware convention, when the CPU32 receives simultaneous
interrupt requests of the same level from more than one SIM source (including external
devices), the periodic interrupt timer is given the highest priority, followed by the IRQ
pins.
5.8.4 Interrupt Processing Summary
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
A. The CPU32 finishes higher priority exception processing or reaches an instruc-
tion boundary.
B. The processor state is stacked. The S bit in the status register is set, establish-
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111;
ADDR[19:16] = %1111, which indicates that the cycle is an interrupt
acknowledge CPU space cycle; ADDR[15:4] = %111111111111;
ADDR[3:1] = the priority of the interrupt request being acknowledged; and
ADDR0 = %1.
3. The request level is latched from the address bus into the IP mask field in
the status register.
D. Modules that have requested interrupt service decode the priority value on
ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration
by IARB contention takes place.