MOTOROLA
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
MC68336/376
8-6
USER’S MANUAL
8.4.7 Dedicated Analog Supply Pins
VDDA and VSSA pins supply power to the analog subsystems of the QADC module.
Dedicated power is required to isolate the sensitive analog circuitry from the normal
levels of noise present on the digital power supply. Refer to Tables A-11 and A-12 for
more information.
8.4.8 External Digital Supply Pin
Each port A pin includes a digital open drain output driver, an analog input signal path,
and a digital input synchronizer. The VSS pin provides the ground level for the drivers
on the port A pins. Since the QADC output pins have open drain type drivers, a dedi-
cated VDD pin is not needed.
8.4.9 Digital Supply Pins
VDD and VSS provide the power for the digital portions of the QADC, and for all other
digital MCU modules.
8.5 QADC Bus Interface
The QADC can respond to byte, word, and long word accesses, however, coherency
is not provided for accesses that require more than one bus cycle.
For example, if a long word read of two consecutive result registers is initiated, the
QADC could change one of the result registers between the bus cycles required for
each register read. All read and write accesses that require more than one 16-bit
access to complete occur as two or more independent bus cycles.
Normal reads from and writes to the QADC require two clock cycles. However, if the
CPU32 tries to access locations that are also accessible to the QADC while the QADC
is accessing them, the bus cycle will require additional clock cycles. The QADC may
insert from one to four wait states in the process of a CPU32 read from or write to such
a location.
8.6 Module Configuration
The QADC module configuration register (QADCMCR) defines freeze and stop mode
operation, supervisor space access, and interrupt arbitration priority. Unimplemented
bits read zero and writes have no effect. QADCMCR is typically written once when
software initializes the QADC, and not changed thereafter. Refer to D.5.1 QADC Mod-
ule Configuration Register for register and bit descriptions.
8.6.1 Low-Power Stop Mode
When the STOP bit in QADCMCR is set, the clock signal to the A/D converter is dis-
abled, effectively turning off the analog circuitry. This results in a static, low power con-
sumption, idle condition. Low-power stop mode aborts any conversion sequence in
progress. Because the bias currents to the analog circuits are turned off in low-power
stop mode, the QADC requires some recovery time (tSR in APPENDIX A ELECTRI-
CAL CHARACTERISTICS) to stabilize the analog circuits after the STOP bit is
cleared.
336376UMBook Page 6 Friday, November 15, 1996 2:09 PM