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参数资料
| 型号： | MC68HC05C8AP |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 78/116页 |
| 文件大小： | 781K |
| 代理商： | MC68HC05C8AP |
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Serial Peripheral Interface (SPI)
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
64
Freescale Semiconductor
10.5.2 Serial Peripheral Status Register
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of data transfer between the
processor and external device. If SPIF goes high and if SPIE is set, a serial peripheral interrupt is
generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an
access of the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited.
WCOL — Write Collision Bit
The write collision bit is set when an attempt is made to write to the serial peripheral data register while
data transfer is taking place. If CPHA is 0, a transfer is said to begin when SS goes low and the transfer
ends when SS goes high after eight clock cycles on SCK. When CPHA is 1, a transfer is said to begin
the first time SCK becomes active while SS is low. The transfer ends when the SPIF flag gets set.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access
to SPDR.
Bit 5 — Not implemented
This bit always reads as 0.
MODF — Mode Fault Flag
The mode fault flag indicates that there may have been a multi-master conflict for system control and
allows a proper exit from system operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects
the internal serial peripheral interface system in these ways:
An SPI interrupt is generated if SPIE = 1.
The SPE bit is cleared. This disables the SPI.
The MSTR bit is cleared, thus forcing the device into the slave mode.
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to
the SPCR. Control bits SPE and MSTR may be restored by user software to their original state after
the MODF bit has been cleared.
Bits 3–0 — Not Implemented
These bits always reads as 0.
Address: $000B
Bit 7
654321
Bit 0
Read:
SPIF
WCOL
0
MODF
0000
Write:
Reset
000000
U
= Unimplemented
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
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