参数资料
型号: MC68HC05C8AP
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封装: PLASTIC, DIP-40
文件页数: 86/116页
文件大小: 781K
代理商: MC68HC05C8AP
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
71
Chapter 12
Instruction Set
12.1 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The
instructions include all those of the M146805 CMOS (complementary metal oxide silicon) Family plus one
more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the
contents of the accumulator (A) and the index register (X). The high-order product is stored in the index
register, and the low-order product is stored in the accumulator.
12.2 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for flexibility in accessing data. The
addressing modes provide eight different ways for the CPU to find the data required to execute an
instruction. The eight addressing modes are:
Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
12.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP).
Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
12.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the
accumulator or index register. Immediate instructions require no operand address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
12.2.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the
opcode, and the second is the low byte of the operand address. In direct addressing, the CPU
automatically uses $00 as the high byte of the operand address.
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