参数资料
型号: MC68HC05C9EFB
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封装: QFP-44
文件页数: 87/144页
文件大小: 1628K
代理商: MC68HC05C9EFB
Resets
RESET Pin
MC68HC05C9E
Advance Information
MOTOROLA
Resets
47
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (tRL). However, to
differentiate between an external reset and an internal reset (generated
from the COP or clock monitor), any externally driven reset must be
active (logic 0) for at least eight tcyc.
Figure 5-2. Power-On Reset and RESET
RESET
OSC1
(2)
INTERNAL
CLOCK
(1)
INTERNAL
ADDRESS
BUS
(1)
V
DD
INTERNAL
DATA
BUS
(1)
t
RL
NEW
PCH
NEW
PCL
OP
CODE
OP
CODE
PCH
PCL
t
CYC
4064
t
VDDR
DUMMY
$3FFF
NEW
PC
NEW
PC
$3FFE
NEW
PC
NEW
PC
$3FFE
$3FFF
$3FFE
DUMMY
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is meant to represent only time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
NOTE 4
4. RESET outputs VOL during 4064 power-on reset cycles.
NOTE 3
t
CYC
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