参数资料
型号: MC68HC05RC18DW
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封装: SOIC-28
文件页数: 108/124页
文件大小: 457K
代理商: MC68HC05RC18DW
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT)
General Release Specification
MC68HC05RC18 Rev. 2.0
84
Carrier Modulator Transmitter (CMT)
MOTOROLA
9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3)
The 12-bit MBUFF and SBUFF registers are accessed through three 8-
bit registers, MDR1, MDR2, and MDR3. MDR2 and MDR3 contain the
least significant eight bits of MBUFF and SBUFF respectively. MDR1
contains the two most significant nibbles of MBUFF and SBUFF. In
many applications, periods greater than those obtained by eight bits will
not be required. Splitting the registers up in this manner allows the user
to clear MDR1 and generate 8-bit periods with just two data writes.
MDR1
Address $0015
Bit 7
654321
Bit 0
Read:
MB11
MB10
MB9
MB8
SB11
SB10
SB9
SB8
Write:
Reset:
Unaffected by Reset
MDR2
Address $0016
Bit 7
654321
Bit 0
Read:
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
Write:
Reset:
Unaffected by Reset
MDR3
Address $0017
Bit 7
654321
Bit 0
Read:
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Write:
Reset:
Unaffected by Reset
Figure 9-8. Modulator Data Registers (MDR1, MDR2, and MDR3)
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