参数资料
型号: MC68HC05RC18DW
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封装: SOIC-28
文件页数: 65/124页
文件大小: 457K
代理商: MC68HC05RC18DW
Interrupts
Core Timer Interrupt
MC68HC05RC18 Rev. 2.0
General Release Specification
MOTOROLA
Interrupts
45
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.6.3 Carrier Modulator Transmitter Interrupt (CMT)
A CMT interrupt is generated when the end of cycle flag (EOC) and the
end of cycle interrupt enable (EOCIE) bits are set in the modulator
control and status register (MCSR). This interrupt will vector to the
interrupt service routine located at the address specified by the contents
of memory locations $3FF8 and $3FF9. Note that the CMT will not
generate any new interrupts while the chip is in wait mode, regardless of
the state of the status register (MCSR).
4.7 Core Timer Interrupt
This timer can create two types of interrupts. A timer overflow interrupt
occurs whenever the 8-bit timer rolls over from $FF to $00 and the
enable bit TOFE is set. A real-time interrupt occurs whenever the
programmed time elapses and the enable bit RTIE is set. Either of these
interrupts vectors to the same interrupt service routine, located at the
address specified by the contents of memory locations $3FF6 and
$3FF7.
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