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参数资料
| 型号： | MC68HC05SR3FB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | QFP-44 |
| 文件页数： | 36/96页 |
| 文件大小： | 3143K |
| 代理商： | MC68HC05SR3FB |
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MC68HC05SR3
Freescale
5-5
RESETS AND INTERRUPTS
5
5.2.2
Maskable Hardware Interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the
I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
5.2.2.1
External Interrupt (IRQ)
The external interrupt IRQ is controlled by two bits in the Miscellaneous Control Register ($0C).
INTE — INTerrupt Enable
1 (set)
–
External interrupt IRQ is enabled.
0 (clear) –
External interrupt is disabled.
The external IRQ is default enabled at power-on reset.
INTO — INTerrupt Option
1 (set)
–
Negative-edge sensitive triggering for IRQ.
0 (clear) –
Negative-level sensitive triggering for IRQ.
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the Condition Code Register is
set. This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents in $1FFA-$1FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register
$0C
KBIE
KBIC
INTO
INTE LVRE
SM
IRQ2F IRQ2E 0001 0000
TPG
39
05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM
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