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参数资料
| 型号： | MC68HC05SR3FB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | QFP-44 |
| 文件页数： | 44/96页 |
| 文件大小： | 3143K |
| 代理商： | MC68HC05SR3FB |
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MC68HC05SR3
Freescale
6-3
TIMER
6
6.2
Timer Control Register (TCR)
The TCR enables the software to control the operation of the timer.
TIF — Timer Interrupt Flag
1 (set)
–
The timer has reached a count of zero.
0 (clear) –
The timer has not reached a count of zero.
The timer interrupt flag is set when the 8-bit counter decrements to zero. This bit is cleared on
reset, or by writing a “0” to the TIF bit.
TIM — Timer Interrupt Mask
1 (set)
–
Timer interrupt request to the CPU is masked (disabled).
0 (clear) –
Timer interrupt request to the CPU is not masked (enabled).
A reset sets this bit to one; it must then be cleared by software to enable the timer interrupt to the
CPU. This timer interrupt mask only masks timer interrupt request to the CPU, and does not affect
counting of the 8-bit counter or the setting of TIF.
TCEX — Timer Clock EXternal
TINE — Timer INput Enable
These two bits selects the source of the timer clock. Reset or power-on clears these bits to zero.
PRER — PREscaler Reset
Writing a “1” to this write-only bit will reset the prescaler to zero, which is necessary for any new
counts set by writing to the Timer Data Register.This bit always reads as zero, and is not affected
by reset.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$09
TIF
TIM
TCEX
TINE
PRER
PRE2
PRE1
PRE0
0100 -100
TCEX
TINE
Clock Source
00
Internal clock to timer
01
“AND” of internal clock and TIMER pin to timer
10
Input clock to timer disabled
11
TIMER pin to timer
TPG
47
05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM
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相关代理商/技术参数 |
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|---|---|
| MC68HC05SU3A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Fully static chip design featuring the industry standard 8-bit M68HC05 core |
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