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参数资料
| 型号： | MC68HC05SR3FB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | QFP-44 |
| 文件页数： | 38/96页 |
| 文件大小： | 3143K |
| 代理商： | MC68HC05SR3FB |
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MC68HC05SR3
Freescale
5-7
RESETS AND INTERRUPTS
5
5.2.2.2
External Interrupt 2 (IRQ2)
The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt
IRQ2 behaves similar to IRQ except it is edge-triggered only.
IRQ2E — IRQ2 Enable
1 (set)
–
External interrupt IRQ2 is enabled.
0 (clear) –
External interrupt IRQ2 is disabled.
IRQ2F — IRQ2 Flag clear
This is a write-only bit and always read as “0”.
1 (set)
–
Writing a “1” clears the IRQ2 interrupt latch.
0 (clear) –
Writing a “0” has no effect.
When a negative-edge is sensed on IRQ2 pin, an external interrupt occurs. The actual processor
interrupt is generated only if the I-bit in the CCR is also cleared. When the interrupt is recognized,
the current state of the processor is pushed onto the stack and the I-bit in the CCR is set. This
masks further interrupts until the present one is serviced. The latch for IRQ2 is cleared by reset
or by writing a “1” to the IRQ2F bit in the MCR in the interrupt service routine. The interrupt service
routine address is specified by the contents in $1FF8-$1FF9.
5.2.2.3
Timer Interrupt
The timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. The
interrupt enable and flag for the timer interrupt are located in the Timer Control Register.
TIM — Timer Interrupt Mask
1 (set)
–
Timer interrupt is disabled.
0 (clear) –
Timer interrupt is enabled.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register
$0C
KBIE
KBIC
INTO
INTE LVRE
SM
IRQ2F IRQ2E 0001 0000
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer Control Register (TCR)
$09
TIF
TIM
TCEX TINE PREP
PR2
PR1
PR0
0100 -100
TPG
41
05SR3.Book Page 7 Thursday, August 4, 2005 1:08 PM
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