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参数资料
| 型号： | MC68HC05SU3AFB |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | QFP-44 |
| 文件页数： | 52/80页 |
| 文件大小： | 328K |
| 代理商： | MC68HC05SU3AFB |
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MOTOROLA
7-10
MC68HC05SU3A
CPU CORE AND INSTRUCTION SET
7
Table 7-8 M68HC05 opcode map
Bit
manipulation
Branch
Read/modify/write
Contr
ol
Register/memor
y
BTB
BSC
REL
DIR
INH
IX1
IX
INH
IMM
DIR
EXT
IX2
IX1
IX
High
0123456789
A
B
C
D
E
F
High
Lo
w
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Lo
w
0
0000
553533659
234543
0
0000
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
R
T
I
SUB
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
1
0001
553
6
234543
1
0001
BRCLR0
BCLR0
BRN
RT
S
CMP
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
2
0010
553
11
234543
2
0010
BRSET1
BSET1
BHI
MUL
SBC
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
3
0011
55353365
10
234543
3
0011
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
SWI
CPX
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
4
0100
55353365
234543
4
0100
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
5
0101
553
234543
5
0101
BRCLR2
BCLR2
BCS
BIT
3
BTB
2
BSC
2
REL
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
6
0110
55353365
234543
6
0110
BRSET3
BSET3
BNE
R
O
R
ORA
R
ORX
R
O
R
OR
LD
A
LD
A
LD
A
LD
A
LD
A
LD
A
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
7
0111
55353365
2
45654
7
0111
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TA
X
ST
A
S
TA
ST
A
S
TA
ST
A
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
8
1000
55353365
2234543
8
1000
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
CLC
EOR
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
9
1001
55353365
2234543
9
1001
BRCLR4
BCLR4
BHCS
R
O
L
R
OLA
R
OLX
R
O
L
R
OL
SEC
ADC
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
A
1010
55353365
2234543
A
1010
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
B
1011
553
2234543
B
1011
BRCLR5
BCLR5
BMI
SEI
ADD
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
C
1100
55353365
2
23432
C
1100
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
RSP
JMP
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
D
1101
55343354
2656765
D
1101
BRCLR6
BCLR6
BMS
TST
A
TSTX
TST
NOP
BSR
JSR
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
REL
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
E
1110
553
2
234543
E
1110
BRSET7
BSET7
BIL
ST
OP
LDX
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
F
1111
5535336522
45654
F
1111
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
W
AIT
TXA
STX
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
1
INH
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
F
1111
3
0
0000
SUB
1I
X
Opcode
in
he
xadecimal
Opcode
in
binar
y
Address
mode
Cycles
Bytes
Mnemonic
Leg
end
Abbre
viations
f
or
address
modes
and
register
s
BSC
BTB
DIR
EXT
INH
IMM
IX
IX1
IX2
REL
A
X
Bit
set/clear
Bit
test
and
br
anch
Direct
Extended
Inherent
Immediate
Inde
xed
(no
offset)
Inde
xed,
1
b
yte
(8-
bit)
offset
Inde
xed,
2
b
yte
(16-
bit)
offset
Relativ
e
Accumulator
Inde
xregister
Not
implemented
TPG
54
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