
Input/Output (I/O) Ports
Port D
MC68HC08GP32A MC68HC08GP16A
Data Sheet
MOTOROLA
Input/Output (I/O) Ports
129
12.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D
pins.
PTD7–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of each port D
pin is under the control of the corresponding bit in data direction register D.
Reset has no effect on port D data.
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD7/T2CH1–PTD6/T2CH0 pins are the TIM2 input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the
PTD7/T2CH1–PTD6/T2CH0 pins are timer channel I/O pins or general-purpose
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input capture/output
compare pins. The edge/level select bits, ELSxB and ELSxA, determine
whether the PTD5/T1CH1–PTD4/T1CH0 pins are timer channel I/O pins or
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE
bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When
the SPE bit is clear, the PTD2/MOSI pin is available for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When
the SPI enable bit, SPE, is clear, the SPI module is disabled, and the
PTD1/MISO pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins
that are being used by the SPI module. However, the DDRD bits always
determine whether reading port D returns the states of the latches or the states
Address:
$0003
Bit 7
654321
Bit 0
Read:
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Write:
Reset:
Unaffected by reset
Alternate
Function:
T2CH1
T2CH0
T1CH1
T1CH0
SPSCK
MOSI
MISO
SS
Figure 12-13. Port D Data Register (PTD)