
Timer Interface Module (TIM)
Advance Information
MC68HC(9)08XK48 — Rev. 4.0
252
Timer Interface Module (TIM)
MOTOROLA
16.4.1 Timer Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, PTE3/TCLK. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS2–PS0, in the
timer status and control register select the TIM clock source.
16.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the timer counter into
the timer channel registers, TCHxH:TCHxL. The polarity of the active
edge is programmable. Input capture latency can be up to three bus
clock cycles. Input captures can generate TIM CPU interrupt requests.
16.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests or TIM DMA service requests.
16.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the timer channel registers.
An unsynchronized write to the timer channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a timer overflow interrupt routine to write a new, smaller output
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