
Preliminary Electrical Specifications
Advance Information
MC68HC(9)08XK48 — Rev. 4.0
318
Preliminary Electrical Specifications
MOTOROLA
21.6 MC68HC08XK48 and MC68HC908XK48 DC Electrical Characteristics
(VDD = 3.0 Vdc ± 10%)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = – 1.0 mA) all ports
VOH
VDD – 0.8
——
V
Output low voltage
(ILoad = 0.8 mA) all ports
VOL
——
0.4
V
Input high voltage
All ports, IRQs, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input low voltage
All ports, IRQs, RESET, OSC1
VIL
VSS
—
0.2 x VDD
V
VDD supply current
MC68HC08XK48
Run(3)
Wait(4)
Stop(5)
MC68HC908XK48
Run(3)
Wait(4)
Stop(5)
IDD
—
4
2.5
5
4
2.5
5
mA
A
mA
A
I/O ports high-impedance leakage current
IIL
——
± 10
A
Input current
IIn
——
±1
A
Capacitance
Ports (as input or output)
COut
CIn
—
12
8
pF
POR re-arm voltage(6)
VPOR
0
—
200
mV
POR reset voltage(7)
VPORRST
0
700
800
mV
POR rise time ramp rate(8)
RPOR
0.02
——
V/ms
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C only.
3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with PLL and LVI enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the power-on reset is released, RST must be driven low externally until minimum
VDD is reached.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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