
Clock Generator Module (CGMB)
CGMB During Break Interrupts
MC68HC(9)08XK48 — Rev. 4.0
Advance Information
MOTOROLA
Clock Generator Module (CGMB)
135
7.8.2 Stop Mode
The STOP instruction disables the CGMB and holds low all CGMB
outputs (CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
7.9 CGMB During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
If this mode is desired during reset, the reset conditions of BCS and
PLLON must be set. If this mode is desired for use in applications where
no crystal is used, the BCS and PLLON bits must not be clearable.
During a large frequency change, the software must allow a stabilization
time. The CGMXCLK signal will always reflect the crystal clock, so the
value of CGMXCLK upon removing the crystal will reflect the value of the
OSC1 pin. If OSC1 is floating, the module could consume significant
power and the output of the CGMXCLK signal would be indeterminate.
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Freescale Semiconductor, Inc.
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