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| 型号： | MC68HC11ED0CP2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 49/108页 |
| 文件大小： | 1672K |
| 代理商： | MC68HC11ED0CP2 |
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Operating Modes and On-Chip Memory
Operating Modes
MC68HC11ED0 — Rev. 1.0
Technical Summary
Operating Modes and On-Chip Memory
4.3.3 Expanded Operating Mode
In expanded operating mode, the MCU has a 64-Kbyte address range
and, using the expansion bus, can access external resources within the
64-Kbyte space. This space includes:
On-chip memory addresses
Addressing capabilities for external peripheral and memory
devices
In expanded operating mode, high-order address bits are output on
ADDR[15:8] pins, low-order address bits and the data bus are
multiplexed on ADDR/DATA[7:0]. Refer to Figure 1-1. MC68HC11ED0
The read/write (R/W) and address strobe (AS) signals allow the
low-order address and the 8-bit data bus to be time-multiplexed on the
same pins.
During the first half of each bus cycle, address information is
present.
During the second half of each bus cycle, the pins become the
bidirectional data bus.
AS is an active-high latch enable signal for an external address latch.
Address information is allowed through the transparent latch while AS is
high and is latched when AS drives low. The address, R/W, and AS
signals are active and valid for all bus cycles including accesses to
internal memory locations.
The E clock is used to enable external devices to drive data onto the
internal data bus during the second half of a read bus cycle (E clock
high). R/W controls the direction of data transfers. R/W drives low when
data is being written to the external data bus. R/W will remain low during
consecutive data bus write cycles, such as when a double-byte store
occurs. Refer to Figure 4-1 for an example of address and data
multiplexing.
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