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参数资料
| 型号： | MC68HC11ED0CP2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 52/108页 |
| 文件大小： | 1672K |
| 代理商： | MC68HC11ED0CP2 |
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Technical Summary
MC68HC11ED0 — Rev. 1.0
Operating Modes and On-Chip Memory
Operating Modes and On-Chip Memory
M68HC11 devices to enter single-chip mode) the CPU will remain in
reset until the RESET pin is pulled low then released with appropriate
logic levels applied to MODA and MODB.
IRVNE — Internal Read Visibility/Not E Bit
IRVNE can be written once in any mode. In special test mode, IRVNE
is reset to 1. In all other modes, IRVNE is reset to 0.
In expanded test modes, IRVNE determines whether internal read
visibility (IRV) is on or off.
0 = No internal read visibility on external bus
1 = Data from internal reads driven out the external data bus
In bootstrap mode, IRVNE determines whether the E clock drives out
from the chip.
0 = E driven out from the chip
1 = E pin driven low
PSEL[3:0] — Priority Select Bits
Refer to Section 5. Resets and Interrupts.
4.5 On-Chip Memory
The MC68HC11ED0 contains 512 bytes of on-chip static RAM. There is
no on-chip ROM. Since the MC68HC11ED0 is intended for expanded
mode applications only, reset and interrupt vectors are not contained in
on-chip resources. An external memory must provide these at locations
$FFC0–$FFFF. Refer to Figure 4-3.
Mode
IRVNE Out
of Reset
E Clock Out
of Reset
IRV Out
of Reset
IRVNE
Affects Only
IRVNE Can
Be Written
Expanded
0
On
Off
IRV
Once
Bootstrap
0
On
Off
E
Once
Special test
1
On
IRV
Once
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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