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参数资料
型号： MC68HC16S2CPU25
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, 25.17 MHz, MICROCONTROLLER, PQFP100
封装： TQFP-100
文件页数： 91/104页
文件大小： 812K
代理商： MC68HC16S2CPU25
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
87
Table 47 25.17 MHz AC Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
1
Num
Characteristic
Symbol
Min
Max
Unit
F1
Frequency of Operation2
fsys
4 fref
25.166
MHz
1
Clock Period
tcyc
39.7
—
ns
1A
ECLK Period
tEcyc
318
—
ns
1B
External Clock Input Period3
tXcyc
39.7
—
ns
2, 3
Clock Pulse Width
tCW
15
—
ns
2A, 3A
ECLK Pulse Width
tECW
155
—
ns
2B, 3B
External Clock Input High/Low Time3
tXCHL
19.8
—
ns
4, 5
CLKOUT Rise and Fall Time
tCrf
—5
ns
4A, 5A
Rise and Fall Time (All Outputs except CLKOUT)
trf
—8
ns
4B, 5B
External Clock Input Rise and Fall Time4
tXCrf
—4
ns
6
Clock High to ADDR, FC, SIZE Valid5
tCHAV
019
ns
7
Clock High to ADDR, Data, FC, SIZE High Impedance
tCHAZx
039
ns
8
Clock High to ADDR, FC, SIZE Invalid
tCHAZn
0—
ns
9
Clock Low to AS, DS, CS Asserted5
tCLSA
219
ns
9A
AS to DS or CS Asserted (Read)6
tSTSA
–10
15
ns
11
ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted
tAVSA
8—
ns
12
Clock Low to AS, DS, CS Negated
tCLSN
219
ns
13
AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold)
tSNAI
8—
ns
14
AS, CS (and DS Read) Width Asserted
tSWA
65
—
ns
14A
DS, CS Width Asserted (Write)
tSWAW
25
—
ns
14B
AS, CS (and DS Read) Width Asserted (Fast Cycle)
tSWDW
22
—
ns
15
AS, DS, CS Width Negated7
tSN
22
—
ns
16
Clock High to AS, DS, R/W High Impedance
tCHSZ
—39
ns
17
AS, DS, CS Negated to R/W High
tSNRN
10
—
ns
18
Clock High to R/W High
tCHRH
019
ns
20
Clock High to R/W Low
tCHRL
019
ns
21
R/W High to AS, CS Asserted
tRAAA
10
—
ns
22
R/W Low to DS, CS Asserted (Write)
tRASA
40
—
ns
23
Clock High to Data Out Valid
tCHDO
—19
ns
24
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
tDVASN
7—
ns
25
DS, CS Negated to Data Out Invalid (Data Out Hold)
tSNDOI
5—
ns
26
Data Out Valid to DS, CS Asserted (Write)
tDVSA
8—
ns
27
Data In Valid to Clock Low (Data Setup)5
tDICL
5—
ns
27A
Late BERR, HALT Asserted to Clock Low (Setup Time)
tBELCL
10
—
ns
28
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
tSNDN
050
ns
29
DS, CS Negated to Data In Invalid (Data In Hold)8
tSNDI
0—
ns
29A
DS, CS Negated to Data In High Impedance8, 9
tSHDI
—45
ns
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)8
tCLDI
8—
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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