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参数资料
| 型号： | MC68HC681FN |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 50/88页 |
| 文件大小： | 726K |
| 代理商： | MC68HC681FN |
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Programming and Register Descriptions
4-24
MC68HC681 USER’S MANUAL
MOTOROLA
4
4.3.17 Count Registers (CUR and CLR)
The count upper register (CUR) and count lower register (CLR) hold the most-significant
byte and the least-significant byte, respectively, of the current counter value. These
registers should only be read when the C/T is in counter mode and the counter is stopped.
See Section 3.5 Counter/Timer for additional information.
4.3.18 Counter/Timer Preload Registers (CTUR and CTLR)
The C/T upper register (CTUR) and C/T lower register (CTLR) hold the most-significant byte
and eight least-significant bytes, respectively, of the preload value to be used by the C/T in
either counter or timer mode. The minimum value that can be loaded into the concatenation
of CTUR with CTLR is 000116. Note that CTUR and CTLR are write-only registers and
cannot be read by the CPU.
4.3.19 Interrupt Vector Register (IVR)
This register contains the interrupt vector. When the DUART responds to a valid interrupt
acknowledge (IACK) cycle, the contents of this register are placed on the data bus. At reset,
this register will contain 0F16, which is the M68000 exception vector assignment for
uninitialized interrupt vectors.
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For More Information On This Product,
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