参数资料
型号: MC68HC705C9ACS
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER
文件页数: 153/177页
文件大小: 1941K
代理商: MC68HC705C9ACS
Capture/Compare Timer
Timer I/O Registers
MC68HC705C9A — Rev. 4.0
Advance Information
MOTOROLA
Capture/Compare Timer
77
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Resets clear the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Resets clear the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow.
Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or logic 0
appears on the TCMP pin when a successful output compare occurs.
Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
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