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参数资料
型号： MC68HC705PD6
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封装： QFP-80
文件页数： 17/165页
文件大小： 841K
代理商： MC68HC705PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
REV 1.1
11-11
IDLE
When the idle line detect bit is set, it indicates that a receiver idle line is
detected (receipt of a minimum number of ones to constitute the number of bits
in the byte format). The minimum number of ones needed will be 10 (M=0) or
11 (M=1). This allows a receiver that is not in the wake-up mode to detect the
end of a message, detect the preamble of a new message, or to resynchronize
with the transmitter. The IDLE bit is cleared by accessing the serial
communications status register (with IDLE set) followed by a read of the serial
communications data register. The IDLE bit will not be set again until after an
RDRF has been set; i.e., a new idle line occurs. The IDLE is not set by an idle
line when the receiver “wakes up” from the wake-up mode. Reset clears the
IDLE bit.
OR
When the overrun error bit is set, it indicates that the next byte is ready to be
transferred from the receive shift register to the serial communications data
register when it is already full (RDRF it is set). Data transfer is then inhibited
until the RDRF bit is cleared. Data in the serial communications data register is
valid in this case, but additional data received during an overrun condition
(including the byte causing overrun) will be lost. The OR bit is cleared when the
serial communications status register is accessed (with OR set), followed by a
read of the serial communications data register. Reset clears the OR bit.
NF
The noise ag bit is set if there is noise on a “valid” start bit or if there is noise
on any of the data bits or if there is noise on the stop bit. It is not set by noise on
the idle line nor by invalid (false) start bits. If there is noise, the NF bit is not set
until the RDRF ag is set. Each data bit is sampled three times as described
above in RECEIVE DATA IN and shown in Fig. 5-3. The NF bit represents the
status of the byte in the serial communications data register. For the byte being
received (shifted in) there will also be a “working” noise ag the value of which
will be transferred to the NF bit when the serial data is loaded into the serial
communications data register. The NF bit does not generate an interrupt
because the RDRF bit gets set with NF and can be used to generate the
interrupt. The NF bit is cleared when the serial communications status register
is accessed (with NF set), followed by a read of the serial communications data
register. Reset clears the NF bit.
FE
The framing error bit is set when the byte boundaries in the bit stream are not
synchronized with the receiver bit counter (generated by a “lost” stop bit). The
byte is transferred to the serial communications data register and the RDRF bit
is set. The FE bit does not generate an interrupt because the RDRF bit is set at
the same time as FE and can be used to generate the interrupt. Note that if the
byte received causes a framing error and it will also cause an overrun if
transferred to the serial communications data register, then the overrun bit will
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