参数资料
型号: MC68HC705PD6
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封装: QFP-80
文件页数: 27/165页
文件大小: 841K
代理商: MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
P-DECODER
MC68HC05PD6
12-6
REV 1.1
12.3.3 Address Comparator
The address comparator checks whether the incoming address codeword is
addressed to itself according to the FA2-FA0, FB2-FB0 of the P-Decoder Control
Register and the six user addresses. Both 32-bit codewords in the self-frame will
be received and will be compared to the six user addresses stored in
ADR
A-ADRF. If the 1st 32 bits of received data is not the same as any of the six
addresses, the 2nd 32 bits of received data in the same frame will also be
compared. If the 1st or the 2nd codeword does match, the index of the matched
user address out of the six user addresses and the 2 function bits in the received
address codeword are stored in the RAIR register, subsequent multiple 20 bits of
error-corrected message codewords are also stored in RMIR registers.
12.3.4 Battery Saving Generator
This block generates the battery saving signals that minimize the battery
consumption. Figure 12-5 shows the timing of the battery saving signals in
waiting mode and Figure 12-7 shows the timing in receiving mode.
12.3.4.1 BS1
It controls the main RF circuit ON/OFF. If BS1 is high, the power of RF circuit
should be turned ON. If BS1 is low, the power of RF circuit should be turned OFF.
12.3.4.2 BS2
It is used to discharge the capacitor of the RF circuit. It changes to high
simultaneously when BS1 changes to high and then changes to low after a certain
time interval. This signal is active high.
12.3.4.3 BS3
It controls the ON/OFF of the PLL circuit. PLL circuit should be turned on before
the RF circuit is turned on. The time which BS3 is activated before BS1 can be set
by the PLL1 and PLL0 bit in PDCR1 register. BS3 goes low when BS1 goes low.
PLL1
PLL0
BS3 activate time before BS1
0
0 ms
0
1
9.76 ms
1
0
33.3 ms
1
62.5 ms
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