- 您现在的位置：买卖IC网 > PDF目录69028 > MC68HC705V8FN (FREESCALE SEMICONDUCTOR INC) 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 PDF资料下载
参数资料
| 型号： | MC68HC705V8FN |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 34/172页 |
| 文件大小： | 890K |
| 代理商： | MC68HC705V8FN |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页当前第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页
MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 118
MC68HC705V8 Specification Rev. 2.1
15.5.1.1
Operation
The clock for the digital filter is provided by the MUX Interface clock. At each positive edge
of the clock signal, the current state of the Receiver Physical Interface (RxP) signal is
sampled. The RxP signal state is used to determine whether the counter should increment
or decrement at the next negative edge of the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample
is low. The counter will thus progress up towards ’15’ if, on average, the RxP signal remains
high or progress down towards ’0’ if, on average, the RxP signal remains low.
When the counter eventually reaches the value ’15’, the digital filter decides that the
condition of the RxP signal is at a stable logic level one and the Data Latch is set, causing
the Filtered Rx Data signal to become a logic level one. Furthermore, the counter is
prevented from overflowing and can only be decremented from this state.
Alternatively, should the counter eventually reach the value ’0’, the digital filter decides that
the condition of the RxP signal is at a stable logic level zero and the Data Latch is reset,
causing the Filtered Rx Data signal to become a logic level zero. Furthermore, the counter
is prevented from underflowing and can only be incremented from this state.
The Data Latch will retain its value until the counter next reaches the opposite end point,
signifying a definite transition of the RxP signal.
15.5.1.2
Performance
The performance of the digital filter is best described in the time domain rather than the
frequency domain.
If the level of the RxP signal transitions, then there will be a delay before that transition
appears at the Filtered Rx Data output signal. This delay will be between 15 and 16 clock
periods, depending on where the transition occurs with respect to the sampling points. This
’filter delay’ must be taken into account when performing message arbitration.
For example, if the frequency of the MUX Interface clock (f
MDLC
) is 1.0486 MHz, then the
period (t
MDLC
) is 954ns and the maximum filter delay in the absence of noise will be
15.259us.
The effect of random noise on the RxP signal depends on the characteristics of the noise
itself. Narrow noise pulses on the RxP signal will be completely ignored if they are shorter
than the filter delay. This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition may be delayed
by an amount equal to the length of the noise burst. This is just a reflection of the
uncertainty of where the transition is truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable
symbol length will be detected by the next stage of the MDLC receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length will normally be
detected as an invalid symbol or as invalid data when the frame’s CRC is checked.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC705V8CFN | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC705X4CDW | 8-BIT, OTPROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05X4CDW | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705X4DW | 8-BIT, OTPROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC708KL8FB | 8-BIT, OTPROM, 1.5 MHz, MICROCONTROLLER, PQFP52 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC706P6ACDW | 制造商:Motorola Inc 功能描述: |
| MC68HC708MP16CFU | 制造商:MAJOR 功能描述: |
| MC68HC711D3CFBE2 | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC711D3CFN2 | 功能描述:IC MCU 2MHZ 4K OTP 44-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| MC68HC711D3CFNE2 | 功能描述:8位微控制器 -MCU 8B OTP 192RAM 2 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。