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参数资料
| 型号： | MC68HC711G5CFN |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封装： | PLASTIC, LCC-84 |
| 文件页数： | 148/195页 |
| 文件大小： | 1940K |
| 代理商： | MC68HC711G5CFN |
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RESETS, INTERRUPTS AND LOW POWER MODES
5-4
is supplied, this delay can be inhibited so that processing can be resumed within a few
cycles of a wake-up from STOP mode. When DLY is set, a 4064 E-clock cycle delay is
imposed to allow oscillator stabilization.
CME — Clock Monitor Enable
0 – Clock monitor disabled; a slow clock may be used.
1 – Slow or stopped clocks will cause a clock failure reset sequence.
In order to use both STOP and the clock monitor, the CME bit should be written to zero
prior to executing a STOP instruction and rewritten to one after recovery from STOP.
CR1 and CR0 — COP Timer Rate select bits
The COP system is driven by a constant frequency of E divided by 215. CR1 and CR0
specify an additional divide-by factor to arrive at the COP timeout rate (see Table 5-1).
5.1.6
State After Reset
The MCU mode is a function of the state of the two mode select pins. Enable bits for the ROM and
the COP system are contained in the CONFIG register, which is initialized during reset, and are
dependent on the mode which has been selected. In the single chip, bootstrap and test modes, the
ROM is on; in expanded mode the ROM is off. In the single chip and expanded modes the COP is
on; in bootstrap and test modes the COP is off.
The remainder of the system configuration is controlled via registers. Most of these registers and
control bits are forced to a specific state during reset. If a user requires a different configuration, he
must write different information into these registers.
Most of the configuration state after reset is independent of the MCU mode selected. Those features
which are specifically dependent on the mode are described in the following paragraphs.
CPU — The CPU fetches the restart vector from $FFFE, $FFFF ($BFFE, $BFFF in bootstrap mode
or test mode) during the first two cycles after reset and begins executing instructions. The stack
pointer and other CPU registers are indeterminate immediately after reset, except for the X and I
interrupt mask bits in the CCR, which are set so that interrupt requests will be masked, and the S
bit, also in the CCR, which is set so that the STOP instruction is disabled.
Memory Map — Immediately after reset the internal memory map of the MC68HC11G5 has 16
kilobytes of ROM located at the top of memory from $C000 – $FFFF (except in expanded mode
where the ROM is disabled and these bytes are external accesses), 512 bytes of RAM located at
the bottom of memory ($0000 – $01FF) and 128 bytes of internal register and I/O space located at
($1000 – $107F). If the bootstrap mode is selected, the memory map is the same except for the
addition of a small internal bootstrap ROM which is located at $BF00 – $BFFF. When a vector fetch
occurs in bootstrap mode, the A14 bit is forced low so that the vectors in the bootstrap ROM are
selected. In the test mode, A14 is also forced low during vector fetches but the bootstrap ROM is
not enabled so vectors are fetched from external memory located at $BFC0 – $BFFF.
Parallel I/O — If reset in an expanded mode, the pins used by the parallel I/O functions are dedicated
to the expansion bus and the parallel I/O functions become externally accessed functions to allow
emulation. If reset in single chip mode, the CWOM bit is initialized to zero (Port C not wired-OR
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For More Information On This Product,
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