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参数资料
型号： MC68HC805P18MP
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封装： PLASTIC, DIP-28
文件页数： 82/144页
文件大小： 1292K
代理商： MC68HC805P18MP
Advance Information
MC68HC(8)05P18 — Rev. 2.0
42
Interrupts
MOTOROLA
Interrupts
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The software interrupt
(SWI) is executed the same as any other instruction, regardless of the I
bit state.
When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$3FF0–$3FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location shown in
Table 4-1 will be serviced first.
An return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction
causes the CPU state to be recovered from the stack and normal
processing to resume at the next instruction that was to be executed
when the interrupt took place.
Figure 4-1 shows the sequence of events that occurs during interrupt
processing.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
Interrupts
CPU
Interrupt
Vector
Address
N/A
Reset
RESET
$3FF3–$3FFF
N/A
Software
SWI
$3FFC–$3FFD
N/A
External interrupt
IRQ
$3FFA–$3FFB
TSR
ICF
Timer input capture
TIMER
$3FF8–$3FF9
TSR
OCF
Timer output compare
TIMER
$3FF8–$3FF9
TSR
TOF
Timer overow
TIMER
$3FF8–$3FF9
N/A
Unimplemented
N/A
$3FF6–$3FF7
N/A
Unimplemented
N/A
$3FF4–$3FF5
N/A
Unimplemented
N/A
$3FF2–$3FF3
N/A
Unimplemented
N/A
$3FF0–$3FF1
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For More Information On This Product,
Go to: www.freescale.com
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