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参数资料
型号： MC68HC901FNR2
厂商： MOTOROLA INC
元件分类： 外设及接口
英文描述： MULTIFUNCTION PERIPHERAL, PQCC52
封装： PLASTIC, LCC-52
文件页数： 14/73页
文件大小： 274K
代理商： MC68HC901FNR2
Bus Operation
3-2
MC68HC901 USER’S MANUAL
MOTOROLA
Figure 3-1. Read Cycle Timing Diagram
3.1.2 Write Cycle
To write a register, CS and DS must be asserted, and R/W must be low. The MFP will
decode the address bus to determine which register is selected. Then the register will be
loaded with the contents of the data bus on the next valid falling edge of CLK, and DTACK
will be asserted. When the processor recognizes DTACK, it will negate DS. The write cycle
is terminated when either CS or DS is negated. The MFP will drive DTACK high and place
it in the high-impedance state. The timing for a write cycle is shown in Figure 3-2. Refer to
Section 8.7 AC Electrical Characteristics for actual timing numbers.
Figure 3-2. Write Cycle Timing Diagram
3.2 INTERRUPT ACKNOWLEDGE OPERATION
The MFP has 16 interrupt sources: eight internal and eight external. When an interrupt
request is pending, the MFP will assert IRQ. In a vectored interrupt scheme, the processor
will acknowledge the interrupt request by performing an interrupt acknowledge cycle. IACK
and DS will be asserted. The MFP responds to the IACK signal by placing a vector number
on the data bus. This vector number corresponds to the particular interrupt channel
requesting service. The format of this vector number is further discussed in Section 4.1.2
Interrupt Vector Number.
CLK
R / W
RS1 - RS5
D0 - D7
DTACK
CS
DS
FIGURE - READ CYCLE TIMING DIAGRAM
MC68HC901UM / AD
FIGURE - WRITE CYCLE TIMING DIAGRAM
MC68HC901UM / AD
CLK
R / W
RS1 - RS5
D0 - D7
DTACK
CS
DS
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